Design And Research Of High Performance Low-dropout Regulator For SoC

As an important member of the power management system,the low-dropout regulator has been applied in many fields due to its advantages such as low noise,high precision and large load current.With the continuous development of System on Chip(SoC)technology,the integration of low-dropout regulator in SoC has become an important developing trend.The low-dropout regulator for SoC can not only help to reduce the voltage jitter caused by SoC crosstalk and inductance on transmission line,and improve the load linearity of output voltage,but also significantly reduce the number of chip pins and decrease the cost of the chip.However,the low-dropout regulator for SoC is unable to connect a large capacitor on its output port outside the chip due to the chip area limitation.As a result,the load transient response performance of low-dropout regulator for SoC is also limited.Moreover,many functions of SoC have to be synchronized with clock,requiring to provide large current from the power supply in a short period of time.Thus the load transient response parameters of low-dropout regulator for SoC are generally poor,and improving the load regulation has become a common design goal of low-dropout regulator for SoC.With optimizing the performance of load transient response as the major design goal according to the requirements of an actual SoC project,this thesis adopts the top-down design method,starting from the analysis of the project design indices,through the topology structure design,circuit design,layout design,to the simulation and tapeout test,and completes the research and design of a high performance low-dropout regulator for SoC.The main content of this thesis is summarized as follows.1)The design indices of low-dropout regulator for SoC are analyzed according to the project requirements(for example,two output ports,the load regulation of output ports of analog module power supply and digital module power supply respectively less than 3 and 4,less than 200 mV output voltage ripple,etc.).The design direction is then established,which is optimizing the load transient response performance of low-dropout regulator for SoC.2)By analyzing the previously reported researches on optimizing load transient response performance,the topological structure of low-dropout regulator for SoC suitable for the project requirements is presented,which is based on the mirror output structure for optimizing load transient response performance proposed by other researchers,but adds a secondary feedback loop to make the load able to establish a certain connection with the error amplifier,which are completely separated in the original design.The improved structure can enhance the regulation ability of error amplifier to output voltage while remaining excellent load transient response of the original mirror structure,leading to an improved load regulation ability.3)Based on the topological structure of low-dropout regulator for SoC,the design of low-dropout regulator for SoC is refined to achieve the design goal of the project,including the detailed structures of small modules such as the pass element,error amplifier,secondary operational amplifier and bandgap reference.Individual simulation is carried on each small module,and the results show that: the low-frequency gain of error amplifier after refined design is 75 dB,reaching the design index of the loop gain;the low-frequency gain of secondary operational amplifier is-935.6 mdB,having no influence on the stability of the overall system;the voltage accuracy of bandgap reference is 16.18 ppm/?.4)After completing the initial transistor level design of low-dropout regulator for SoC,the system stability is analyzed.The results show that the system has only one pole within the unit gain bandwidth,while adding a compensation capacitor of 165 pF in the pass element grid,the system stability can be further improved.The compensated structure is thus the whole transistor level structure of low-dropout regulator for SoC.5)The layout design of low-dropout regulator for SoC is also completed.This thesis conducts simulations on performance parameters such as load regulation,load transient response,line regulation,power-supply ripple rejection,loop gain and phase margin by using the designated SMIC CMOS 0.13 ?m process model after extracting the parasitic parameters.Simulation results indicate that the designed low-dropout regulator for SoC meets the design requirements of the actual project.Compared to other designs,our design provides a high performance low-dropout regulator for SoC with better load transient response.Finally,by combining the whole chip requirements and performance requirements of low-dropout regulator for SoC,the overall layout is completed and sent to a certain foundry,and the overall performance tests are conducted on the sample chips after tapeout.Major features of this thesis can be concluded as follows.1)The output voltage ripple of low-dropout regulator for SoC with the improved mirror output structure is less than 167 mV,so the good load transient response performance of original design is retained.2)The load regulation is reduced from 3.813 of the original design to 2.797 of the improved design,so the load transient response performance is improved.3)The separate power supply structure for analog and digital modules has been skillfully combined,the influence of digital module on the quality of the power supply for analog module is isolated,and the voltage fluctuation of analog module power supply is only less than 1 mV with changing transient current of digital module.4)The layout area is 1700 ?m×390 ?m,exhibiting the area saving advantage of our two output ports structure.Other performance parameters of the designed low-dropout regulator for SoC include a power-supply ripple rejection of 49.4 dB@100Hz,a phase margin of 90°,a line regulation less than 0.43%,and so on.