On-chip High-speed Response Low-dropout Linear Regulator Circuit And Design

With the widely applications of portable electronic products, power management requires higher efficiency, smaller area and lower cost, which makes LDO more and more popular. The LDO without off-chip capacitor can be implemented on chip, so that it would become the mainstream according to the development of SOC. The on-chip implement saves the area of PCB, but at the same time it challenges the engineers aggressively. There is strict selection of equivalent series resistor in the traditional architecture to assure the stability of system. Besides, using large output capacitor would afford charge to load circuit when the load current changes a lot.According to the problems, the research designs a single stage regulator with improved load regulation. This architecture has a good transient response without off-chip capacitor. It can achieve stable state as the load circuit varies which it only uses less than 100pF on-chip parasitical capacitor. This design reduces the chip area, so it is applicable to implement of SOC.The chip has been implemented with SMIC 0.18μm 1.8V/3.3V CMOS 1P6M process. The chip area is 1055μm×1300um. The test result shows that the LDO has a good transient response according to transient signal with less than 160ns rising and falling time in present condition and dissipates static current of 20μA at standby mode.