A Fast-response Low-dropout Regulator In 65nm CMOS

The progress of integrated circuit has promoted the rapid development of wireless communication,mobile internet and internet of things,which requires system-on-chip(SoC)to integrate more and more modules and functions,so that the power management technology inside the system chip is very common.In the power management circuit,low-dropout regulator(LDO)has stable output potential,suffers low noise and is easy to be integrated.The traditional structure of LDO needs a large off-chip capacitor at the output to ensure the loop stability and transient characteristics.This is not good for the improvement of SoC integration.Capacitor-less LDO(CL-LDO)can avoid external passive devices,but the stability and transient response need to be optimized.In this thesis,a CL-LDO with high speed transient response,which is used to the power management module in 5G high-speed data conversion interface,is proposed.The proposed CL-LDO is mainly composed of a voltage reference circuit,an error amplifier,a feedback network and a transient response optimization circuit.Optimization is made for improving the loop stability and transient response of this CL-LDO.There are mainly four methods used in this LDO.1.In order to improve the transient response of CL-LDO,a new transient response optimization circuit is proposed.By introducing the auxiliary fast detection and adjustment circuit,the output driving current is adaptively and dynamically adjusted according to the detected overshoot and undershoot voltage of LDO’output.This can reduce the overshoot and undershoot voltage at the output,hence increasing the transient response speed.2.In the design of error amplifier,a two-stage operational amplifier(OP-AMP)is used to compare the reference voltage and feedback voltage,then outputs the amplified comparison result.Compared to other OP-AMP structure,the two-stage OP-AMP is more likely to provide large output swing under the requirement of enough voltage gain.In terms of loop stability,Miller compensation technique with null resistance is used to ensure the loop stability.The on-chip compensation capacitor used in this LDO is 5 pF.3.As for the voltage reference,temperature compensation based on current summing method is utilized to realize a 0.8 V stable voltage reference for the CL-LDO over a wide temperature range.In the layout design,the input transistors of the OP-AMP are placed symmetrically.Pseudo-transistors are also used to further improve the matching performance.The resistive feedback network layout is designed with segmentation-based symmetrical method.Pseudo-resistors are also used for achieving similar peripheral environment.With these above techniques,the CL-LDO circuit is designed with a 65-nm CMOS process.The Cadence tool is used for circuit design,layout design and simulation.The active area of the CL-LDO is 160μm×130μm.With an input voltage that ranges from 1.5 V to 2.5 V,the output voltage is 1.2 V,then the minimum voltage drop is 300 mV.The maximum output load current of this LDO is 10 mA.Under a condition without any current load,the quiescent current of this LDO at 2.5 V input is 87 μpA.By adopting the transient response optimization circuit proposed in this thesis,the CL-LDO output overshoot and undershoot voltages are reduced from the original 68 mV and 94 mV to about 22 mV,when the load current is switched between 100 μA and 10 mA at 1 μs rise and fall time.The output of this LDO can be stable to 0.5%accuracy range in 1.04 μs.