Design Of High Resolution, 11b Pipeline TDC In 40nm CMOS

In electronic instrumentation and signal processing,a Time-Digital Converter is a device for recognizing events and providing a digital representation of the time they occurred.TDC in high energy physics,laser ranging,satellite navigation and other fields have a wide range of applications.In addition,due to the rapid development of semiconductor technology,in the field of radio frequency(RF)wireless communication,TDC can be used as a phase detector,so that the all digital phase-locked loops can replace traditional charge pump phase-locked loops.As the scale of the integrated circuit is larger and larger and process line width smaller and smaller,the design of the high resolution TDC become the current hot research direction gradually.In this paper,the TDC is mainly used in the CMOS image sensor based on the single-photon avalanche diode.As a result,the fluorescence lifetime can be mearsured with the quantitative techniques of time interva.Based on the TDC research achievement at home and abroad,this paper puts forward a novel structure applicable in a variety of situations,which meets the needs of the large dynamic range and the higher accuracy pipeline structure of TDC of 2.5 bit/stage.At the same time,the construction of the architecture from the system to the mixed signal circuit design process has been complemented.In this paper,the TDC,mainly made of a 2.5 bit/stage pipeline structure of TDC has 6 levels and 11 bits.With the interstage of the time amplifier based on SR-latch,which transfers the residue of the last stage to the next level by 4 times with the fixed gain,the pipeline TDC has broken through an inverter delay time limit and realized the door level precision.The residue calibration circuit and the TA calibration circuit can optimize the linearity of the TDC.A new PVT resistance circuit has been proposed to improve the robustness of the whole TDC circuit.This design,based on the Hlmc 40 LP CMOS process design of the TDC circuit and the layout of the key module,has been simulated.The simulation results show that the time resolution of the TDC is 2.4 ps,the dynamic range is 4.9 ns,the precision is 11 bits,the DNL is less than ±0.7LSB,the INL is less than ±2LSB,the power consumption is 33 m W under the power supply voltage of 2.5V/1.1V and the input reference frequency of 20 MHZ.The newly-designed TDC can meet the design requirements.