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Device State Acquisition And Interlock Protection System Based On FPGA

Posted on:2018-07-03Degree:MasterType:Thesis
Country:ChinaCandidate:Y P WangFull Text:PDF
GTID:2322330533460036Subject:Control theory and control engineering
Abstract/Summary:PDF Full Text Request
In ADS(Accelerator Driven Sub-critical System)projects,The IMP takes responsibility for the development of Injector II,which is the intense beam proton accelerators with high operation risk.According to the theoretical calculations,to prevent device damage from continuous impact of intense beam,the response time of beam cut-off should be within 10?s.At the same time,the system should provide the function to obtain and store status data of key devices when failures occur to implement failure location and analysis.The interlock protection system based on the distributed architecture,which is divided into two parts,main control system and front-end sub control system.The function of the sub-system is to acquire the fault signal of the device and transmit to the master control system,and upload the device information to the control room in real time.The function of the main control system is to analysis the signal of the subsystem,and make Chopper cut off the beam,as well as enable the corresponding protection equipment.The device uses the photoelectric conversion modules to convert TTL or switching signals into standard optical signal.The transmission among systems is by optical fiber,and control signals are transmitted by Ethernet.In this paper,the entire interlock protection system architecture is designed based on the FPGA and optical fiber network.With the MIS system of Shanghai Institute of Applied Physics as the master system to emphatically present the design of the hardware board of sub-system,and the photoelectric conversion module.The software design of sub-system is also particularly presented,which is designed to implement and evaluate the function of the interlock protection system,as well as the application of the control program.The function of the whole system and the response time are both tested in detail,which show that the hardware circuit of the interlock protection system meets the design requirements,and all the functions and response time meet the security requirements.
Keywords/Search Tags:FPGA, Photoelectric conversion, Decices state information, Optical fiber transmission, Interlock protection, Ethernet
PDF Full Text Request
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