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Research And Design Of Output Voltage Adjustable Linear Regulator Without Off-chip Capacitor

Posted on:2018-04-19Degree:MasterType:Thesis
Country:ChinaCandidate:H XuFull Text:PDF
GTID:2322330536983300Subject:Communication and Information System
Abstract/Summary:PDF Full Text Request
In recent years,with the promotion and popularization of portable mobile electronic products,the products which shows low standby power consumption,high battery life and high power conversion efficiency become more and more popular.As an important part of these products,the design of power management technology has also got a great development.Low-dropout linear regulator(LDO)is one of the most common product of power management chip.Thanks to its simple circuit structure,low output noise,high output precision and low static power consumption,LDO is widely used in many fields.In the traditional structure of LDO,an off-chip large capacitor is adopted to improve loop stability and transient response characteristics,but a micro-scale large capacitor is difficult to integrate on the chip.At the same time,the use of large external capacitor will increases the area of Printed Circuit Board(PCB)and the cost of chip application.Therefore,LDO without an off-chip capacitor become the focus of attention of the industry.In this paper,an output voltage-regulated LDO without off-chip capacitor is analyzed and designed,which mainly includes bandgap reference,oscillator,quadruplet decoder,over temperature protection,over current protection and error amplifier.In order to obtain a higher accuracy of the reference voltage,bandgap reference circuit uses chopper op-amp and low-pass filter structure to reduce the op-amp input offset voltage and noise.The error amplifier uses the damping factor control(DFC)technique to improve the stability of the system.Meanwhile,the push-pull output is employed to increase the output voltage swing and transient response speed.The over temperature protection circuit uses a hysteresis comparator to make the temperature generate a hysteresis threshold,avoiding oscillations near the upper limit temperature.Based on the CSMC 0.18 um process,the design and simulation of the circuit are carried out by using Cadence Spectre tool.The simulation results show that,in the input range of 2 ~ 4.0 V,the maximum output current of designed LDO is 62 mA,the output voltage can be chosen as 1.596 V 1.697 V,1.793 V and 1.888 V,load regulation rate is 0.014uV/m A and power supply regulation rate is 0.679mV/V.At 2.0V and 3.3V power supply,LDO low-frequency power supply rejection ratio is 52 dB and 68 d B.Due to temperature protection module,the main circuit will be turned off at 131 ? and be re-opened at 111 ?.When the load current exceeds 62 mA,the over current protection circuit will start and closes the main circuit.In summary,the designed LDO can be applied in the digital-analog hybrid chip.
Keywords/Search Tags:LDO, without off-chip capacitor, Low noise chopping bandgap, damping coefficient control, CSMC
PDF Full Text Request
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