Hardware Design Of Low-Frequency Phased-Array Doppler Velocity Log

At present,DVL is widely used as the ship speed measurement and navigation equipment.Its basic working principle is the Doppler principle,that is,there is Doppler frequency shift between the received echo signal and the transmitted signal.Velocity can be calculated by Doppler frequency shift which can be obtained by measuring the frequency of the echo signal.Doppler velocity log can get the relative velocity of the carrier to the water flow and the absolute velocity of the carrier to the seabed.However,due to the fact that the current Doppler log works at a relatively high frequency as well as other limitations,it is difficult to achieve velocity measurement in deep sea area,for example,the measurement of the bottom velocity in the deep sea area can be very difficult.This paper mainly completes the hardware design and implementation of 60 kHz phase-controlled Doppler velocity log.The mechanism of Doppler velocity measurement is briefly introduced.The design and debugging of transmitter and receiver of Doppler velocity measurement system as well as the programming and debugging of digital signal processing circuit test program are mainly described.The hardware circuit of the velocity log includes two parts: analog circuit and digital circuit.The analog circuit is divided into transmitting circuit,receiving circuit and power supply circuit.The transmitting circuit realizes the matching of the power amplifier circuit and the transducer,so high efficiency and high power signal emission is realized.The receiving circuit improves the form of filter circuit,high pass elliptic filter and the low-pass elliptic filter are used in series to achieve the purpose of filtering with high Q.Power supply circuit that uses a variety of DC-DC power modules to reduce the interference between the various parts of the circuit has achieved power supply effect with digital-analog isolation and high-low power isolation.Digital signal processing circuit using three C6000 DSP chip and one CPLD work together to improve the work ability.System debugging and pool experiment are carried out after the design and debugging of each part of the circuit.Experimental results show that the system works well and stably,and can satisfies various technical indexes.