Design Of Power Hardware In The Loop Simulator For Brushless DC Motor

Brushless DC motor(BLDCM)has the advantages of high efficiency,high power density and high reliability,and is widely used in many fields including aerospace.However,in practical applications,BLDCM from design to production takes a long time and testing different specifications of the BLDCM need to install the corresponding platform,the steps are very cumbersome.The Power Hardware-in-the-loop(PHIL)simulator is an extension of the Signal Hardware-in-the-Loop(SHIL)simulator that not only exchanges voltage and current signals with motor drivers,but also produce real electric power interaction,is one of the most real Hardware in the Loop simulation device.The PHIL simulator can be connected to the actual motor drive instead of the actual motor and can be used for the development of motor drives and verification of control algorithms.Since the actual motor power can be interrogated with the motor driver under test,the PHIL simulator test covers all hardware of the motor driver and does not require hardware modifications to the motor driver under test.The application of the PHIL simulator can greatly simplify the testing of the BLDCM drive without waiting for the process from design to production to fit the corresponding mechanical test bench.However,there are no motor PHIL simulator mature technology and products in China,the actual application needs to buy expensive foreign products.More importantly,the aerospace and other sensitive areas cannot apply the corresponding foreign products,research and development with independent intellectual property rights of the domestic PHIL simulator is particularly urgent.This paper designs a PHIL simulator for BLDCM applications,as follows:First,the BLDCM hardware in-loop simulator model is established,including the position sensor model,BLDCM commutation transient model,BLDCM electrical and mechanical numerical model.Secondly,the overall structure of BLDCM PHIL simulator is constructed,and the voltage detection analog front end and power level current source of BLDCM PHIL simulator are designed.Thirdly,the bandwidth characteristics of the line voltage sampling anti-aliasing filter and BLDCM,BLDCM driver and the bandwidth of the digital signal controller in BLDCM driver are analyzed,and the method of determining the voltage sampling frequency of BLDCM PHIL simulator is analyzed.The Sampling frequency can be low,can significantly reduce the processor performance requirements.Finally,the experimental test of the PHIL simulator is carried out,including the simulation of the front end,the resolver simulator,the power level current source and the BLDCM PHIL simulator.The experimental results verify the effectiveness of the BLDCM PHIL simulator design method proposed in this paper.