Design Of An AES Coprocessor For Near Field Communication Secure Element

In recent years, mobile payment industry becomes a focus of attention for people. As one of the strategic pillars of mobile payment, the Near Field Communication(NFC) Technology has a large market space for development. While the key factor for utilizing NFC Technology to realize mobile payment is to guarantee the security of the customers’ information and properties, the secure element(SE) plays a vitally important role in this respect. Combining the requirements to apply NFC secure element in mobile payment, this issue designed and implemented an AES algorithm coprocessor with high security, low area cost and high throughput.First, this issue stated the application environment and system architecture of the NFC secure element, and had an in-depth analysis of the principles and mathematics foundations of the AES algorithm. To fulfill the high security, low area cost and high throughput requirements for the NFC SE to apply in mobile payment, the following measures are taken to design and implement a well performing AES algorithm intellectual property(IP) core: implementing the S-box in the finite field way, adopting the internal and external mixed pipeline architecture, implementing the shift-rows operation with the 64-bits folding architecture, optimizing the architecture of the AES IP core and adopting a finite state machine with data path to realize the design in order to make the AES IP core support a variety of encryption/decryption key length.Secondly, to apply to the secure element, an interface controller is designed based on the Wishbone Bus Protocol and it makes the AES IP core able to be applied in the secure element system-on-chip architecture directly and conveniently. After that this issue has a systematic elaboration of the design and implementation of the AES coprocessor. The verilog language is used to complete the front-end design and the simulation results, synthesis informations and the physical layout are obtained form the EDA tools. The results synthesized with the UMC 0.18 um COMS technology process shows that the power consumption and area of the AES coprocessor is 21.90 mW and 0.824 mm2 individually.The maximum clock frequency can reach 149.25 MHz and the average power consumption is 1.47mW@10MHz. The highest throughput is 1.82 Gbit/s.Finally, a MIPS processor core is used to build a system on chip to perform the FPGA verification of the AES coprocessor. The verification and test results show that the coprocessor is in good performance and works stably. After compared with other similar designs, it can be found that the designed AES coprocessor meets the design requirements of high security, low area cost and high throughput.