VLSI Design Of JPEG2000 Bit-Plane Decoder

With the rapid development of technology such as computer, communication, network, the digital images are widely used in communications, Internet, healthcare, e-commerce, remote sensing satellites, military, legal, etc., resulting in data range exponentially. The huge amount of data caused great pressure in image processing, storage and transmission, so the image compression technology plays an important role in the digital image applications.JPEG2000 is a kind of image compression standard with superior performance with advantages of having controllable rate, high compression ratio, suitable for network transmission. It is of good applicability for natural images, synthetic images, satellite images, medical images and other kinds of images. Currently there are high-performance JPEG2000 encoder chip "Ya core II" designed by Image Transmission and Processing Research Institute of Xidian University for the aerospace industry. However, there has yet to be a breakthrough in the high-speed hardware implementation of JPEG2000 decoding system. The main reason is that the complex decoding algorithm makes JPEG2000 difficult to meet real-time processing requirements, especially that bit-plane decoded part of JPEG2000 is of high complexity, long development cycle and large processing delay, resulting in high-speed hardware decoding of JPEG2000 system implementation difficulties. Therefore, further study of JPEG2000 bit-plane decoder hardware implementation is of great importance.In conjunction JPEG2000 standard and FPGA hardware platform features the overall objective of this study is to implement JPEG2000 decoding system in Xilinx VC707 development board, with the ingress rate achieving 100 Mbps. The main contents of this paper are as the following two parts:(1)The registers taking column scanning and columns skipped program of the scan window 3×4 are designed and context of samples in column is pre-calculated in this paper. The VLSI architecture of the register window, the context generating and updating and four coding primitive structure and the state transition diagram of three passes are given in this paper. The bit-plane decoded part is implemented by HLS. Compared with the traditional handwritten code development mode, HLS is with advantages of fast development and flexible adjustments, thus the entire bit-plane decoder is implemented by HLS.(2)With in-depth analysis of the processing speed of each part in JPEG2000 decoding systems, efficient storage scheduling scheme is made and the DDR(Double Data Rate SDRAM) controller is completed in this paper.The focus of this paper is bit-plane decoding part as well as research and implementation of DDR memory scheduling part of JPEG2000 decoding system in place. Bit-plane decoder is completed by HLS, to solve the problem of long development cycle of handwritten Verilog/VHDL code and complex development process issues, many kinds of architecture is formed by HLS constraints for different speeds, different resource needs scenarios. After the realization of bit-plane decoder in the development board VC707, export rates is up to 98.1Mbps and resource consumption is less than 3%. The average throughput is increased by 5 times higher than structure before optimization and resource consumption is reduced by more than half. Combined with efficient scheduling scheme of DDR memory,the decoder can decode the image code with ingress rate of 100 Mbps and compression rate of doubleness and fourfold,and can meet general real-time processing requirements.