VLSI Design Of JPEG2000 Decoder

JPEG2000 still image compression standard accessed to people's attention because it has many excellent features. It took the embedded block coding with optimal truncation (EBCOT)and discrete wavelet transform technology(DWT) as the two main technologies. So it has a higher compression ratio for large-size images and a flexible compressed stream compared with the JPEG standard.We introduced the basic principles of JPEG2000 Decoder firstly, And then gave the overall VLSI implementation structure of JPEG2000 Decoder, Including Tier-2 decoder, Bit-Plane-Decoder(BPD), MQ Decoder(MQD), Inverse Discrete Wavelet Transform (IDWT). The implementation of every module and interface had been described. We focused on the JPEG2000 decoder core of the system Bit-Plane-Decoder. we proposed a Stripe-Skip and Stripe-Column Skip arithmetic, The bit plane scaning(BPS) efficiency was improved, We also designed the implementation structure of Bit-Plane-Decoder.The RTL code of the whole JPEG2000 decoder was described by Verilog HDL language. An efficient verification platform was setup. We took the compressed data generated by Jasper software encoder as the stimulation source, then the JPEG2000 decoder which was designed read the compressed data, and was simulated in the VCS emluator.In order to validate the simulation result. We chose the OpenJpeg software decoder as the golden model. This golden model read the same compressed data as the designed JPEG2000 decoder. And then compared the two results from both golden model and JPEG2000 decoder, when the simulation finished. If these two results were the same, so the JPEG2000 decoder was right and can achieved the expected function.At the end, We synthesized the RTL code of JPEG2000 decoder using HJTC 0.18μm CMOS standard cell library. The highest frequency of the design was up to 67.8MHz after simulation and DC synthesis. It can be used for real-time image processing.