Research On Key Modules Of High-speed Serial Transmission

High-speed serial data transfer request data signal transmission line to a single bit in a continuous transmission, and improve transmission bandwidth single data lane approach is to maximize the clock frequency, however, increasing the clock frequency will cause serious interference between the high frequency component loss is serious, and 0 or 1 will transmit data in a long continuous signal value is smaller than the moment the reverse transition, DC-balanced transmission line deteriorates, the receiver becomes more difficult to lock the clock, will reduce the data transmission rate.The paper made the following tasks:1. Based on the data flowing through the sending end of the transmission line and each module receiving end of a detailed description of the proposed transmission side the entire circuit design architecture, divided into digital and analog circuit section, define the overall design and each module port signals, performance indicators each digital and analog circuit design methods.2. For DC balance issues,Using semi-custom digital circuit design approach to achieve phase compensation FIFO, 8B/10 B encoder and serializer, where the encoding process into 3B/4B and 5B/6B encoding and set the valid data characters and control characters select signal, and running disparity indication signal.effectively disrupting the continuous transmission of the data length of 0 or 1, the receiving end provides sufficient locked clock signal transition;3. For inter-symbol interference, designed with pre-emphasis driver circuit to compensate loss in the high frequency component of the transmission line. In a conventional LVDS driver circuit on the basis of(a) adding Shunt components, the total resistance is reduced, increasing the load current;(2) adding a second current source, the load current value;(3) CML two parallel circuits, and one output will be delayed some time to achieve increased signal.Using semi-custom digital circuit design method implement digital circuits, using Verilog HDL description of the encoding process, functional simulation using Modelsim to do, and in 130 nm CMOS process,use DC mapping software to integrate and export its gate- level netlist, the export area, power, timing, and other reports.The pre_emphasis design, in 130 nm CMOS process, uses Virtuoso software to implements the analog circuit structure, in Hspice simulation soft ware 3.125 Gbps transmission bandwidth can be reach, add a suitable capacitor, adjust the W/L of mos tube, reducing glitches,and to achieve optimal results.