Design And Implementation Of Serial RapidIO Interface For A High Performance Processor

In order to meet the challenges of the rapid development of embedded processing technology,while meeting the future development needs of embedded systems.The world’s leading semiconductor manufactures jointly developed a can achieve any topology and point to point operation,efficient,highly reliable and the efficient congestion control of high-speed interconnect protocol-Rapid IO.Rapid IO interconnect architecture to meet the embedded infrastructure in the application of a wide range of needs to meet the embedded system interconnection requirements.In this paper,through the following aspects of research,fully based on the high-performance processor on the Rapid IO interface design and verification work.1.In response to the large amount of data throughput in the processor application scenario,it is required to implement the Rapid IO interface in the chip to meet the design specifications.The processor is a dual-core high-performance SOC,the CPU core based on Power PC architecture,and has a wealth of on-chip peripherals,including Rapid IO interface,PCIE interface and Ethernet interface.The processor can be embedded network,telecommunications aerospace and defense storage.The industrial and many other applications to bring breakthrough performance,connectivity features and integration.2.Through the in-depth study of Serial RapidIO protocol,we can understand the realization of the protocol,understand the meaning and composition of the specific fields in the logical layer,the transport layer and the physical layer,and design the Rapid IO interface to meet the performance requirements of the processor.Complete transaction package encapsulation,link channel port initialization,transaction packet sending and receiving,and 8B/10 B encoding and decoding operations.Which focuses on the physical layer of the key circuit to optimize the design,including the realization of the channel state machine,8B /10 B coding unit of the correct code and serial and parallel conversion circuit applications,so that the final design of interface comply with Rapid IOv1.3specification.3.In this paper,the VIP platform component based on the solution to verify the interface,the use of advanced VIP components and UVM platform to build a VIP component based on the UVM verification platform to verify high-speed Serial Rapid IO interface.Through the perfect verification plan in the host mode and the slave mode fully verified,and ultimately meet the performance requirements of the processor.VIP component which is a universal verification IP,you can widely verify a variety of peripheral interfaces.UVM methodology is a validation platform development framework based on the System Verilog class library,which allows auditors to build functional verification environments with standardized hierarchies and interfaces using their reusable components.