The Design And Verification Of A Multi-port DDR2 Controller Based On AMBA Bus

The vast development of information technology brings people great convenience,and also demand the electronic devices achieve higher performance.To achieve the faster process speed,higher density,and lower power consuming,the So C design guide become more and more popular.A complete So C design is make up by every function module in it,and among all electronic system,the RAM module is an integral part.Whatever the temporary save of the CPU’s computing data,or to move data from device to another device,the RAM space all need to be used.And the performance of the RAM device usually become the bottleneck of a system.So,it’s obvious that a high performance So C chip also need a high performance RAM module.The RAM controller IP based on technology of reused IP core,become the essential part to achieve high performance RAM module.Beside,because of the great cost of both on money and time to fabricate chip,the verification of the So C front design is extremely important,and the simulation and verification will always take the majority time of the front design of a chip.So it’s important to customize the verification scheme with both high efficiency and low difficulty,and the verification work needs to be cover all the function of the module.The article focus on the design and verification of a multiport DDR2 controller which used in a So C chip based on AMBA architecture.To fulfill the demand of this So C chip which the RAM controller needs to be read by both AXI bus and AHB bus in the same time,the author give out an solution to modify and added on the base of some IP core offerd by 3rd party company and design a RAM controller.This RAM controller can let the device on the different bus to access the system RAM space,and the priority parameter of both port could be modified.Using the same solution,the max number of the port could reach to 16,and this function great wide the application range of the RAM controller.Besides,for the verification work of this multiport RAM controller,author using Verilog HDL,build a high efficiency testbench,and design the bus function model in the testbench.To cover the function of this controller,the author specifically code the verification software.During the FPGA verification,dule to the phy module couldn’t achieve on FPGA,author design a substitute module of the original phy.The new fpga_phy could imitate the function of the original phy but could also achieve on FPGA.The article contain the summary of the work,based on these work,the author give out a scheme of the design and verification of the similar RAM controller IP.In the end of the article,author also summary the deficiency and the problem in word,and give some suggestion of the future work.