Design Verification Testbench Of CAN Bus Controller Based On UVM

With the rapid development of integrated circuit technology,the scale and complexity of the chip and the workload of chip verification is rapidly increasing.The traditional verification method is difficult to meet the current needs.The complexity of the verification work is low at early stages,and the direct test incentive approach can well meet the needs of the verification work.Therefore,Verilog was used as the verification language at that time,and the verification platform construction scheme also depended on the initial,task provided in Verilog,function and other statements.With the development of the era,the development of higher level of abstraction of verification language has become a general trend.The System Verilog language has emerged as the times require.In order to further shorten the chip's R&D cycle,major EDA vendors have jointly launched an efficient verification scheme,the UVM verification methodology.The UVM verification methodology establishes a large class library based on the System Verilog language,which greatly simplifies the verification while improving the abstraction of verification and improves the efficiency of verification.Based on this,the UVM verification methodology has gradually become the mainstream methodology in the verification industry.This paper analyzes the CAN bus controller module in the research project of the internship unit and builds a matching UVM verification platform.In the process of building the platform,the excellent mechanisms such as factory,sequence,phase,and config_db integrated in UVM are fully applied,and a large number of randomized components are added to make the verification environment closer to the real work situation.In order to reduce the complexity of each sub-module and improve the portability of the verification platform,a layered design approach is adopted.When the test items of the verification platform are changed,only different test case modules need to be replaced without modifying the verification platform itself.Ensure the stability of the verification platform.Based on the in-depth understanding of CAN2.0 protocol,this paper designed a variety of test cases including: standard packet format transmission test,extended format packet transmission test,self-test mode test,reset test,bus shutdown test,etc..In the test case running process,the automatic result comparison method is used,in which the monitor module is responsible for monitoring the output of the CAN bus controller,and through the scoreboard module for comparison,to determine whether the test result meets expectations.In addition,in order to ensure the accuracy of the verification results,this paper selects representative simulation waveforms for each test item for detailed analysis.After the verification task is completed,the final coverage results are counted.The coverage rate reaches 97.26%,the branch coverage rate reaches 98.3%,the expression coverage rate reaches 94.2%,the overall coverage rate reaches 97.22%,and the functional coverage rate reaches 100%,this result meet the expectations.In the aspect of verifying the portability of the platform,the traditional method of manually setting up the verification platform is time-consuming and error-prone.This paper uses Perl language to complete the automatic generation of the verification directory structure and the verification platform module,ensuring the standardization of the verification project.At the same time,it helps verification engineers quickly complete the framework design of the verification platform.In addition,the automatic generation of script code for the verification platform designed in this paper provides a user-selectable platform design scheme.During the actual project application process,the internal modules of the verification platform can be deleted according to requirements,which greatly improves the verification efficiency.