A Transient-Enhanced Capacitor-less Low-Dropout Regulator Design

Integrated voltage regulator has become of high power density, high reliability and high efficiency. As a member of regulators, low dropout regulator (LDO) has been widely used in portable products, which develops in the direction of System on Chip (SoC). For its simple application and easy integration, the capacitor-less LDO is the best choice. Compared with the conventional LDO, capacitor-less LDO has a great drawback of stability and transient response, which is the most challenging part. Design consideration, design method and design flow of transient-enhanced capacitance-less LDO are discoursed in this thesis in detail.Researches include transient response, stability of capacitor-less LDO, design flow of analog Integrated Circuit and the basic specification of LDO.At first, the specification of LDO is reviewed and summarized. Each spec. of LDO is researched, updated and corrected, including the definition, influencing factor and the relationship of each other.Secondly, the design flow of analog integrated circuit has been researched. All level modeling type of analog integrated circuit is researched, especially for the macro-modeling. Detail macro model of operation amplifier is presented, based on which, the mixed macro model with"Macro model + Transistor level circuit"is introduced to increase the design efficiency and facility.Thirdly, the loop stability of the capacitor-less LDO has been researched. A modified Damping Factor Control (DFC) frequency compensation method is proposed. The new LDO scheme provides full range ac stability from 50μA to 100mA load current by only one pole frequency lower than unity gain frequency. Detail calculation and derivation for the DFC technology based cap-less LDO are given out. The behavior and macro model are built, which are the guide to design and realize the transistor level circuits. At last, the transient response of capacitor-less LDO has been researched. The transient response of capacitor-less LDO is analyzed in comparison with the traditional LDO first. The influence factor to the transient response of capacitor-less LDO is analyzed, based on which a novel transient-enhanced method for capacitor-less LDO is proposed. Basic operational amplifier, inverter and push-pull driver are introduced to increase the slew rate current of the pass device gate when the load current is changed, so the transient response is enhanced.A 100mA, 1.8V, transient-enhanced capacitor-less LDO voltage regulator was designed in the HHNEC 0.25μm standard CMOS technology, which was applied to a base band SoC chip in wireless sensor network nodes. Detail design flow is given out, including circuit spec. derivation, sub-circuits dividing, transistor level circuit design, and simulation and so on. The simulation shows that the LDO consumes only 44uA of ground current with a dropout voltage of 50mV under 100mA load current. The maximum over-shoot voltage is 90 mV and the output voltage error is only 0.039 % due to the line regulation and load regulation.