Research On The Quantization Of Texture Mapping Unit Architecture Based On SystemC TLM Model

With the increase of the complexity and application scope of the system-on-chip design and the continuous improvement of product features and performance requirements,the project design cycle has become an important consideration for the availability of products.Traditional system verification is performed at the register transfer level.Although more accurate simulation data can be provided,it will also take a lot of time and subsequent problems will be modified to increase the cost again.While the complex SOC system verification accounts for 60%-70% of the entire design time,it is imperative to complete system verification as soon as possible.In order to improve the abstraction level and simulation speed of the graphics processor architecture,this paper uses System C language to model at the transaction level.The transaction level modeling with a high level of abstraction successfully bridges the communication between modules and modules within the time span.Stripping,parallel computing of data and processes,simulation speed greatly improved.The model has good compatibility,and can embed the simulation platform for structural design and verification of the hardware functionality,as well as software development.After ensuring the functionality is achieved,the abstraction level is added successively to reduce the cycle precision and statistical parameters at the later stage,and the performance evaluation under different architectures is also satisfied.Therefore,the model in the early design of the architecture verification and the later hardware performance evaluation play a key role,is conducive to speed up the graphics processor as the core of the design,development and application.Texture mapping plays a major role in improving the authenticity of the generated image and is a key part of real-time image pipeline generation.Texture mapping can achieve high-performance textures at a small cost.This paper first studies texture filtering and anti-aliasing in the texture mapping process,and analyzes the characteristics of texel access in different texture filtering modes to improve the parallelism of texture mapping.Improve the operating speed.At the same time,draw on Mip Map pre-filtering technology to optimize the mapping effect and save computing time.Based on the theoretical research,the structure of the texture mapping and the construction of the pipeline are completed,and the functional correctness of the texture map is verified using System C modeling.However,due to the increase of the degree of parallelism,the texture bandwidth becomes the key bottleneck of the entire flow level.Therefore,the quantitative research on the texture cache module is also the main research content of this paper.For the storage wall problem of the texture Cache structure,this article focuses on the selection,analysis and results of Hakura’s evaluation parameters for cache,and proposes the study of the configuration parameters of each Cache in the second-level cache,through the Cache capacity and the line in L1.The analysis of size,relevance,and the configuration of the size of the cache for matching with L2 is compared quantitatively.Finally,the performance under different modes is evaluated based on the cache hit rate and execution time to select the optimal parameters.This paper implements a quantitative evaluation of the Cache so that the pipeline based on the quad texture is not constrained by memory access.