EDAC Algorithm Implementation Method And Chip Storage Reinforcement Template Design

The next 20 years will be a strategic opportunity period for the development of China’s space satellites.However,Single Event Upsets effects have always existed in the space environment.This will cause data errors in the memory of spacecrafts.In order to ensure the reliability of spacecraft operations,it is common Both are using anti-irradiation processors on spacecraft.For many years,many of China’s anti-irradiation processors have been imported.Therefore,the development of more independent anti-irradiation processors is of great significance for the long-term reliance on imports from our aerospace-class processors.However,in the design of autonomous anti-irradiation processor,due to the diversity of morphological and functional features stored on-chip,its logical reinforcement work is more complicated and the workload is larger.This thesis builds a fast generation algorithm that supports any bit-width parity check matrix based on the widely used SEC-DED code Hsiao code.According to the requirements for hard disk storage on the chip,an on-chip storage hardening template tool is designed.This tool can automatically and quickly generate the code required for the storage body reinforcement,thereby improving the efficiency of the designer and the large amount of storage consolidation in the actual project.The task has a certain significance.This thesis first designs and implements a fast generation algorithm for 4-4096 bits arbitrary bit width Hsiao code check matrix.The non-equivalent generative vector is introduced,and the vector cyclic shift method and the construction method of the tail matrix are designed.The overall description of the algorithm,an example of the algorithm,and the evaluation of correctness and advancement were performed.The RTL implementation of the Hsiao codec module was completed;then an on-chip memory reinforcement template was designed.Based on the memory-enforced socket layer that can be used for high-efficiency bank error correction and reconstruction,this thesis proposes a special processing mechanism for data writeback,small granularity write,refresh and other issues,and solves data correlation processing and busy signal setting.And other key issues.The codec module of Hsiao code is embedded in this socket layer,and the different port request memory banks are processed and parameterizable and configurable design is performed;then the codec module of Hsiao code is based on the verification environment of SV and The storage-reinforced socket-layer module was verified and a timing analysis was performed after DC synthesis.The final results showed that the design function was correct and the timings met the requirements in the actual project.Finally,based on the Python language under Linux,the design of this thesis is implemented and the scripting tool is processed.Including the human-machine interaction interface that can input parameters,after inputting the parameters,the Hsiao code encoding and decoding code,code of different types of storage and reinforcement sockets,and the supporting two verification environment codes can be output in the corresponding path.The code can be used directly.At present,the tool has been applied in the latest project.After statistics,a total of 56 different types of codes have been output in 13 parts.No problems have been found so far,which greatly reduces the workload of design and verification and improves work efficiency.