Research And Implementation Of Resisting SEU Technology Based On Commercial Chip Spaceborne Signal Processing Platform

With the rapid development of satellite communication technology,the aerospace-grade chip with anti-noise capability for space radiation is increasingly difficult to meet the demand of processing capability for spaceborne platform.Currently,the COTS(Commercial off-the-shelf)route based on commercial chip spaceborne platform design technology becomes a hot research topic at home and abroad.Space radiation noise is the critical factor to impact the reliability of satellite application system.SEU(Single Event Upset),the most common type of radiation noise effect,can directly results in run-time errors and system failures.Space-grade chip,with special hard reinforcement design,has a strong anti-noise ability for space radiation;Primarily commercial chip set for high-density,high-capacity,low voltage and high speed processing,does not consider the design with anti-noise capability.Whether it's able to take advantage of high-speed and large-capacity of commercial chip and transform them into an ability of anti-noise soft reinforcement to adapt spaceborne applications platform,is the industry's continuous efforts in the direction.This paper focuses on issues related to this technology research,the main work includes:1.SRAM-based FPGA SEU sensitivity of research and experiment.This paper regards FFT based on IP core as target algorithm.By using the method of analog SEU sensitivity fault injection test,the internal Slice,RAM and other major resources of SRAM-based FPGA will be tested in SEU sensitivity fault injection test.The statistic data analyzes the impact of SEU effects to target algorithm error and failure probabilities in different resource,summarizes SEU sensitivity to a variety of FPGA resources,and provides scientific basis for guiding subsequent soft reinforcement reinforcing priorities and reinforcement design method.2.SEU sensitivity research and experiments with fine-grained FPGA resources.This paper regards target algorithm created independently as a test subject and uses refined fault injection method to analyze the SEU's impact on processing resources in logic unit(LU).The fine understanding to sensitivity of SEU impact on FPGA is obtained.We give a detailed analysis of the test results and conclusions.3.For FPGA anti-SEU soft reinforcement design.This paper designs a soft reinforcement method which combines triple modular redundancy(TMR)with dynamic reconfiguration.Among them,the TMR design based on SEU sensitivity test conclusion for FPGA,gives strong reinforcement to resources with high sensitivity,gives weak reinforcement to resources with weak sensitivity,gives self-healing design which based on whole or partial reconfiguration to the target algorithm.With a relatively small resource consumption,this TMR design improves the anti-SEU ability of target algorithm effectively.Experiments and test results show the effectiveness of the design.