Research On Single Event Effect In FDSOI Devices And SRAM Circuits

Integrated circuits for aerospace application usually work in a harsh space radiation environment,which means they will be bombarded by many high-energy particles in space to cause radiation effects.Both NGDC and the NASA have reported the cause of satellite failures and found that SETs are the leading cause of satellite electronic system failures.With technology scaling down,component integration continues to increase,node capacitance decreases,and circuit operating frequency increases,SETs have a greater impact on the reliability of CMOS integrated circuits.At the same time,radiation-hardened CMOS integrated circuits need to be based on more advanced process nodes to meet the increasing demand of on-board computing.FDSOI technology has become an important choice for the development of radiation-hardened CMOS integrated circuits below 28 nm.Therefore,the SET research for FDSOI devices and circuits is necessary for the development of integrated circuits for future aerospace application,which has aroused strong concern in academia and industry.In this dissertation,the 28-nm FDSOI devices and SRAM circuits are the main research objects.Combined with the three-dimensional TCAD numerical simulation,ground heavy ion irradiation experiment and theoretical analysis method,the SET sensitivity characteristics of FDSOI devices,the impacts of process scaling down and the impacts of temperature,voltage and incident particles on SET and SEU have been syste matically studied.The main work and contribution of this dissertation are described as follows:(1)With the process scaling down,the SET sensitive area and the sensitivity difference between NMOS and PMOS of FDSOI devices is pointed out for the first time.The results show that the NMOS device in the FDSOI process is more sensitive to SET than the PMOS device.The sensitivity difference is significant in the 180-nm process,while the 28-nm process is not obvious.With technology scaling down,the SET sensitivity of NMOS and PMOS in the FDSOI process will be more similar.The area where the FDSOI device is truly sensitive to SET is the drain region close to the gate region,and the drain region will become more sensitive than the gate region with the process scaling down.When the drain contact moves away from the gate direction,the most sensitive region will drift toward the drain region away from the gate,and the amount of charge collection increases.(2)It is proposed for the first time that SET in 28-nm FDSOI devices exhibits a strong anti-temperature effect under low voltage.It is found that the SET pulse width increases linearly with the decrease of the supply voltage when the supply voltage is above 0.6V.However,the SET pulse width increases sharply with the decrease of the supply voltage when the supply voltage is below 0.6V.It is first discovered that the 28-nm FDSOI device exhibits strong SET temperature sensitivity at low voltage(<0.6V)operation,and the SET pulse width exhibits a significant anti-temperature effect.However,SET is not sensitive to temperature at normal voltage(1V)operation.By analyzing the impacts of temperature and supply voltage on the device saturation current and charge collection,the correlation mechanism between SET and temperature and voltage is revealed.(3)The impacts of incident position,LET threshold,and incident angle on the SEU of 28-nm FDSOI SRAM are evaluated comprehensively.The TCAD simulation results show that the most sensitive region under the 28-nm process is the drain region of the pull-down NMOS transistor,which is different with the conclusion that the drain region is not sensitive in the FDSOI SRAM cell above 45-nm process.It is found that the LET threshold for SEU in the 28-nm FDSOI SRAM cell is approximately 1.8 Me V-cm²/mg.The heavy ion irradiation experiments show that the influence of incidence parallel to the gate is greater than incidence vertical to the gate,but their SEU cross sections are both on the order of 10^-10.There is no MCU in vertical incidence,and there are few SEMUs in30°and 60°incidences.The MCU cross section is on the order of 10^-12.(4)It is found that SEU in 28-nm FDSOI SRAM circuits has a slight anti-temperature effect,the voltage dependence is affected by the LET of particles,and the best body bias is zero bias.Combined with three-dimensional TCAD numerical simulation and heavy ion irradiation experiments,it is found that the SEU in the 28-nm FDSOI SRAM circuit exhibits a slight anti-temperature effect.The SEU cross section is slightly smaller on the high temperature and the anti-temperature effect is weaker when the incident particle LET is higher.When the particles with lower LET(O ions)are used,the SEU cross section increases significantly with the supply voltage decreasing.However,the SEU cross section has no evident correlation with the supply voltage when particles(Ge ions)with higher LET are used.The body bias for the smallest SEU cross section is ZBB,that is,the body biases of NMOS and PMOS devices are all grounded.This dissertation focuses on the SET sensitivity difference of devices and the change of charge collection mechanism,which are caused by the new structure introduced by FDSOI technology.The impact of process scaling down on SET sensitivity characteristics is also considered.At the same time,aiming at the harsh temperature conditions of the space environment and the low-voltage and low-power operation characteristics of the FDSOI technology,the impacts of voltage and temperature on the SET sensitivity are studied.Aiming at the higher soft error contribution rate of SEU in CMOS integrated circuits of FDSOI process,the most typical SRAM circuit is selected as the research object.The influence of various factors such as particle incidence and circuit working state on the SEU cross section is analyzed.These works provide a reliable reference and raw data for systematically and comprehensively understanding the SET of FDSOI process,and provides significant theoretical guidance for the future radiation-hardened CMOS integrated circuit design of FDSOI process.