Research On Airbus Single Event Upset Effect Test System Based On Dynamic Reconfiguration

With the development of electronic technology and semiconductor industry,the number of airborne electronic devices is increasing.Large-scale integrated circuits(ICs)represented by static random access memory(SRAM)field programmable gate array(FPGA)are widely used in the aviation field because of high integration,high operation rate and repeatable writing.However,due to the improvement of semiconductor technology,the size and threshold voltage of devices on ICs are decreasing.This increases the risk of single event effect in integrated circuits caused by airborne radiation environment and threatens the safe flight of aircrafts.Therefore,aviatic single event effect has attracted wide attention from civil aviation administrations and aviation industry.Considering the inconvenience of using the flight-carrying experiment and the ground-based experimental device simulation test to verify the aeronautical single event upset effect,it is necessary to propose a more efficient method for the evaluation of the aeronautical single event upset effect.In this paper,the SRAM-based FPGA which is easy to generate single event upset effect on aircraft is selected as the research object.According to the mechanism of single event upset effect,the test system of single event upset effect in aviation was studied based on dynamic reconfiguration technology.Firstly,through the study of the atmospheric radiation environment under aircraft flight conditions,it is determined that atmospheric neutrons are the main radiation source for the single event upset effect of airborne electronic equipment.Based on Boeing empirical model,a kind of aeronautical single particle based on co-evolution is proposed.The method of inverting the fault data is combined with the SRAM based FPGA device model to determine the inversion rate and randomly generate the inversion fault location to provide fault data input for the aircraft single event upset effect.Secondly,the mechanism of the aeronautical single event upset effect of the SRAM-based FPGA is studied and determined.Using dynamic reconfiguration technology to achieve the equivalent single event upset effect in the way of fault injection;once again,to meet the requirements of dynamic reconfiguration technology,Altium Designer software is used to independently design and build a multi-FPGA hardware test platform,and complete fault injection.FPGA logic design realizes the equivalent aeronautical single event upset effect of SRAM-based FPGA device by fault injection.Then use LabVIEW to complete the visualization of the host computer interface development,realize the process control,information processing and display function of the test system;Take The ARINC429 bus is the test object,and the test circuit is designed to verify the aeronautical single event upset test system.The function failure rate is obtained under the target condition,and the validity of the test system is verified.