Design And Research Of 1553B Bus Remote Terminal Based On FPGA

In recent decades,the technology in the aerospace industry has developed rapidly.The increasingly stringent design requirements for the internal equipment of aerospace systems are miniaturizing,generalizing and scalable.The trend of development has been to use of FPGA to implement bus communication protocols.The MIL-STD-1553 B bus is a centralized control mode,command/response multiplex serial data bus standard with high reliability and flexibility.With the wide application of the 1553 B bus in the aerospace and military fields,the development of the 1553 B protocol IP core is increasingly important to reduce the application cost of the bus,improve the flexibility of application development,achieve the localization of the 1553 B protocol chip,get rid of dependence on foreign chips,reduce engineering risks and Cost.After in-depth analysis of the 1553 B bus protocol,this paper designs and implements the FPGA-based 1553 B remote terminal with top-down design.First,this paper analyzes the 1553 B bus protocol,especially focusing on the function of the 1553 B remote terminal and its communication mode,then determines the overall architecture of the remote terminal design and performs module division for the remote terminal.Secondly,the general-purpose Manchester II codec is designed and implemented based on the 1553 B bus protocol and the Manchester codec principle.The design idea and state transition process of the encoder and decoder are introduced in detail.At the same time,the protocol processor module of the remote terminal is designed and implemented.The design of the protocol state machine,channel selection module and dual-port RAM is elaborated.The state transition process of the protocol state machine is introduced.Furthermore,the timing simulation and comprehensive optimization of each module and the whole of the designed remote terminal are carried out.The timing simulation results verify that the logic function of the design is correct.Finally,the test simulation card is used to build the test platform to perform broad level verification.The communication test results prove that the design has realized the overall function of the remote terminal and can complete the normal communication of the system.Each module is designed and implemented by Verilog HDL hardware description language in this paper.It is integrated and simulated by Xilinx’s dedicated FPGA development environment ISE14.1 and ISE Simulator and XST.