FPGA Simulation Unit Design For Intelligent Substation Training System

Smart substation has become the main form of state grid corporation system construction substation.In order to improve the ability of front-line relay protection and automation team technicians to operate and maintain the digital secondary system and equipment of smart substation,the state grid corporation of China has started the training for front-line employees of smart substation,which has become the next focus of state grid corporation of China.At present,the training system of intelligent substation in China is still in the primary stage compared with that in foreign countries.The purpose of this thesis is to design a set of simulation training device that can be used in the field of substation.The Programmable hardware part of the device is the Field Programmable Gate Array(FPGA)chip.The work of this paper is to make full use of the advantages of FPGA chip programmability,abundant memory resources and parallel computing,use FPGA to complete the second-side simulation calculation,and solve the problem of excessive consumption of software platform resources.This thesis focuses on the realization of secondary side protection simulation calculation in FPGA.Firstly,the model information of the secondary side protection device in the actual substation is analyzed,and the simulation calculation method of the protection device is explained.Then,computing elements for different data types are designed on FPGA.In the upper computer,a automatically generated top-level file is designed to form the engineering file of secondary side simulation calculation.Finally,the script was used to compile and download the project files in FPGA.To ensure the work of the device,the thesis studies the internal and external communication of FPGA.According to the data flow direction,this thesis divides the external communication unit into three small links,which are sending and receiving,caching and transmission of digital message.The digital message sending and receiving work is based on the gigabits network interface.The cache part of the digital message is designed on the basis of calling its IP core with the help of DDR2 chip.The digital message transmission part is based on the PCIE interface data transmission,through the analysis of its hierarchical structure,on the basis of the IP core to complete the DMA simulation design.The internal communication unit mainly solves the interconnection problem of multiple FPGA chips.The last part of the thesis is the function verification of the whole device.The real test of the communication unit is carried out,and the signal captured in the test conforms to the expectation.At the same time,the whole function of the device is tested,and the result shows that the device can be simulated correctly.