Design And Analysis Of Power Array For 3D PDN

In order to extend the development of Moore’s law,the chip begins to develop into 3D integration technology.In 3D integration technology,three-dimension power delivery network(3D PDN)is responsible for providing a stable voltage for the entire chip,which will bring larger current density and more complicated current switching mode in some special cases,causing serious power integrity problems and influencing the function of the chip.Therefore,a stable 3D PDN design is the key to 3D integration technology.For the research of 3D PDN,this thesis carries out the following work:In order to analyze the DC voltage drop in 3D PDN design,the analysis of 3D PDN based on parasitic resistance distribution is applied,and the influence of current distribution on DC voltage drop is analyzed in this thesis.The analysis shows that the DC voltage drop of 3D PDN can be effectively reduced by choosing the appropriate design of 3D PDN according to the current distribution when designing 3D PDN.The thesis further discusses the influence of through-silicon-vias(TSV)on the parasitic resistance distribution of 3D PDN.Under the same design resources,the design with distributed TSVs on the 3D PDN can effectively reduce the average parasitic resistance of the 3D PDN by 43%,which is beneficial to reduce the DC voltage drop of the 3D PDN under the average current distribution.The design with densely distributed TSVs can reduce the minimum parasitic resistance of the 3D PDN,which is beneficial to reduce the DC voltage drop under the uneven current distribution.The “microring-resistance” method,superposition effect and segmentation method are used to analyze the parasitic resistance distribution of 3D PDN.The "microring-resistance" method and the superposition effect constitute the calculation of the parasitic resistance distribution of the single-layer 3D PDN,and the segmentation method is used for the calculation of the parasitic resistance distribution of the multi-layer 3D PDN.The total error of the "microring-resistance" method is 2.83%,compared with the result of the software extraction,when calculating the parasitic resistance distribution of the single-layer 3D PDN of 500um*500um with one TSV.The topology of the double-layer 3D PDN is discussed by the segmentation method.The analysis indicates that it is necessary to optimize both the TSV distribution of the own layer and the TSV connection of the lower layer to reduce the parasitic resistance of the 3D PDN.The design rules for TSV spacing is analyzed in 3D PDN design.The analysis shows that reducing P/G TSVs spacing and increasing P/P TSVs(or G/G TSVs)spacing can mitigate the simultaneous switching noise(SSN)caused by TSV’s parasitic inductance.The 3D PDN simulation structure of 248um*248um is established,and the SSN is analyzed.The design with distributed capacitors on the 3D PDN is applied to improve the noise-reduction by 64%.In this thesis,a co-simulation platform based on full-wave simulation and circuit simulation is built,and the frequency characteristics and transient characteristics of low dropout regulator(LDO)on 3D PDN are analyzed.In the co-simulation scheme,the 3D PDN enhances the output stability of LDO.Further analysis shows that the design scheme with multiple LDOs can effectively reduce the DC voltage drop and voltage recovery time of the 3D PDN,but it can not reduce the overshoot voltage during circuit switching,and it will cause the stability problem of LDO.Finally,the effect of the capacitance designed on the 3D PDN on the LDOs’ performance is analyzed.The analysis indicates that larger capacitance can effectively reduce the overshoot voltage of 3D PDN during switching from heavy load to light load,but reduce the frequency response bandwidth of LDO and greatly increase the recovery time of LDO.Therefore,the performance optimization of LDO should be taken into account when using capacitor to improve the performance of 3D PDN.