Design And Implementation Of Testbench For ARINC429 Bus Interface Module Based On UVM

ARINC429 bus is one of the most commonly used communication buses in the global avionics system.It has the advantages of simple structure,stable performance and strong anti-jamming ability.It is widely used in civil aviation and military aircraft.The ARINC429 bus interface module validated in this paper belongs to the peripheral interface module on So C.It communicates with CPU through APB interface,receives differential bit stream of external input and sends differential bit stream to peripherals according to ARINC429 bus protocol with A/D and D/A circuits.The efficient and complete functional verification of ARINC429 bus interface module is of great significance for ensuring aviation safety.With the development of advanced process technology,the complexity of So C functions and the scale of integration are increasing.The traditional Verilog HDL-based testbench has been unable to meet the growing verification requirements.Based on the module-level verification of ARINC429 bus interface module on So C,this paper analyses the advantages and disadvantages of current mainstream verification language and verification methodology,deeply studies the structure of current mainstream UVM testbench and advantages of UVM verification methodology,chooses to build an abstract,automated and reusable testbench based on UVM to achieve high efficiency and completeness functional verification.The structure and function of ARINC429 bus interface module are analyzed in depth,and the working principle of each sub-module is studied.On this basis,the verification function points are extracted.Aiming at the verification requirement of function points,the testbench of ARINC429 bus interface module based on UVM is designed and implemented by object-oriented programming and transaction-level modeling.Driver,monitor,reference model,scoreboard,assertion and register model are designed.The testbench innovatively adopts automatic updating aggregation parameters,which can timely adjust parameters of testbench during the simulation process and improve the automation of testbench,and avoid the non-independence of reference model caused by the use of register model to read register configuration.Based on this testbench,directional testcases and random testcases are constructed around verification function points to simulate and verify,covering normal and abnormal working scenarios,and the verification results are analyzed.Collect code coverage and functional coverage,and analyze the uncovered points of test cases to ensure the completeness of verification work.Engineering practice shows that compared with the original Verilog testbench,the UVM testbench designed in this paper has clear hierarchy,supports real-time automatic comparison of data,can accurately locate errors and print relevant information when the verification results are wrong,saves the debugging time of defects and shortens the verification cycle.After the simulation,the code coverage is more than 90%,and the uncovered code is redundant;the function coverage is 100%,and the verification function points are all covered.The code coverage and the function coverage reach the expected goal.At the same time,some components of the testbench have been successfully transplanted to other projects and have good reusability.