Research On Acceptance Evaluation Technology Of Bare Chip For Solid State Relay

The semiconductor device is the core of modern electronic products,and the bare chips are the modes of semiconductor devices before package.As long as the higher requirements of the performance of integrated circuits for the electronic products functions,bare chips had been found wide application nowadays.It is necessary to evaluate and control quality of bare chips scientifically and effectively.Therefore,this thesis studies the acceptance evaluation method of bare chips in entering the factory based on the quality control requirements of bare chips in the employer of the author.Firstly,completing the optimization of quality evaluation project for bare chip based on the types and characteristics of semiconductor plastic package devices.According to different types of semiconductor bare chip devices,the evaluation test circuit,evaluation test flow and quantitative evaluation calculation method for quality evaluation are proposed.According to the different types of bare chips used in solid-state relays,the specifications for acceptance and evaluation of bare chips are compiled.Secondly,based on the evaluation process of bare chips given herein,in association with electrical properties of bare chips and the characteristics of chip surface mater ials,a special interface for testing and evaluation is designed.According to the characters of the bare chip,designed for four evaluations,such as:(1).The bare diode chip,the bare triode chip and the bare voltage regulator chip are common interfaces,which can be used for evaluation of bare diode chip,the bare triode chip and the bare voltage regulator chip whose length and width are within 0.6mm×0.6mm.(2).According to difference in size and power of bare FET chips,a general evaluation interface for low-power FET chips and a general evaluation interface for medium-power FET chips are designed respectively.The general evaluation interface for bare chips of low-power FET can be used for evaluation of chips with dimensions within 2mm×1.8mm.For chips with dimensions within 9.2mm×6.6mm,the general evaluation interface for bare chips of medium power FET can be adopted.(3).According to on-resistance of different FET,the resistance of the evaluation interface and the thermal resistance,the evaluation calculation is carried out,corresponding aging current is set for each FET,and quantitative calculation method is given.With target to the particularity that bare LED chips and bare photodiode array chips should be used together,a double-layer clamp interface is designed to realize multi-specifications connection of interface to test quality of bare chip.At the same time,the evaluation interfaces of all designed chips can pack the tested bare chips and be filled with inert gas,in order to remove the effect of surface oxidation of bare chips on test results under high-temperature test environment.Finally,regarding contamination of bare chips from assembly before evaluation test,assembly process of evaluation are optimized and improved,so that relia ble assembly of bare chip without use of flux and cleaning on evaluation interface can be realized,and factory-level operation specifications on evaluating assembly of bare chip is established.It can be concluded from huge evaluation data and results of evaluation that,the research results of the thesis satisfied the requirements of quality control,and realize the goal of evaluating bare chips in the factory independently.