Design And Implementation Of Audio Compression System In Voyage Data Recorder

In order to strengthen the safety supervision and management of ships and ensure the safety of the crew and the person and property at sea,according to the resolution of the International Maritime Organization(IMO)Resolution A.861(20)and the relevant regulations of the Maritime Safety Administration of the Ministry of Communications of China,international navigation and coastal navigation Ships must install a Voyage Data Recoder(VDR,commonly known as marine black box).VDR is an intelligent recording instrument for real-time recording and storage of important data of ship systems during navigation and related information about the surrounding marine environment.According to IMO related standards,the sound of key compartments such as the cockpit and the audio signal VHF of the ship communication are the data that must be recorded by the VDR.When an accident occurs in a ship,the audio data in the VDR is an important basis for investigating and analyzing the cause and process of the accident.Therefore,it is important to use the appropriate platform and algorithm to compress these audio data,so that VDR can store more data in a limited space.In this paper,the current situation of VDR voice compression is analyzed,and according to the relevant standards of IMO and International Electrotechnical Commission IEC61996 document,it's determined that the heterogeneous multi-core system-on-chip Zynq of ARM+FPGA is used as the core processor of VDR voice compression system,and the MP3 is used as the compression algorithm of this system.The overall structure of VDR audio compression system is completed by software and hardware collaborative design.In this paper,Zynq's ARM processor system(PS)is used to control audio acquisition and Ethernet devices,and the Multi-channel voice compression involving a large number of parallel computations is implemented in hardware in Zynq's programmable logic(PL),making full use of the advantages of FPGA's parallel computing ability and stable and reliable operation.Due to the complexity of the MP3 algorithm,the implementation of the algorithm requires a large amount of hardware resources.According to the principle of MP3 compression coding algorithm and the requirement of VDR for the playback quality of voice signal,this compression coding algorithm is optimized to save the quality of voice playback while saving the hardware resources needed for algorithm function realization.And then according to the principle of the optimized MP3 algorithm,combined with FPGA parallel computing,pipeline and other technical means,the FPGA hardware structure design and simulation of the compression coding algorithm is completed in the Vivado integrated development environment.Aiming at the problem of VDR multi-channel audio data transmission,the scheme of audio data transmission between heterogeneous cores is designed,and the high-speed transmission of audio data from FPGA to ARM is realized.The audio data Ethernet transmission program is completed on the PS end of ZYNQ,and the host computer receiving software is programmed and simulated,to simulate the reception and storage of audio data in black box.Finally,Zedboard is used as the core verification platform to verify and test the acquisition,compression,encoding,transmission and storage of two audio data.The test results meet the relevant standards.