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Research On Reliability Analysis And Hardened Design Of Cache System In Microprocessor

Posted on:2021-05-07Degree:MasterType:Thesis
Country:ChinaCandidate:G P LiFull Text:PDF
GTID:2392330611499123Subject:Integrated circuit engineering
Abstract/Summary:PDF Full Text Request
The rapid development of integrated circuit design and manufacturing process has made the feature size smaller and smaller,especially after entering the nano-scale process,the threshold voltage of the circuit is further reduced,the number of integrated transistors continues to increase,and the soft error rate rises sharply.The Cache system is an important part of aerospace applications.It stores a large amount of data.If it is not protected,it is susceptible to errors caused by radiation.The Cache system has high requirements on speed,area and power consumption,so it is very meaningful to effectively protect the Cache system at a small overhead.For the Cache system,according to the different working modes of Cache,the paper designs the corresponding reinforcement method.For the write direct mode,the interleaved parity check method is adopted to deal with the problem of multi-bit inversion.For the write-back mode,error checking and correction hardening methods are commonly used,but the delay of the codec has a relatively large performance overhead for caches that require high speed.The paper proposes a reinforcement strategy for redundant backup.By adding a backup Cache(Replication Cache,RCache),the dirty cacheline is backed up to RCache,and parity check with low latency overhead is used for data error detection.When an error is detected,a signal of a forced miss is issued.For dirty cachelines,data is obtained from the underlying memory,and for dirty cachelines,data is obtained from RCache.Based on the OR1200 processor platform,the thesis separately verifies the feasibility of three different reinforcement methods,namely interleaved parity check,Hamming code reinforcement and redundancy backup designed in this paper,and verifies the effect of reinforcement.The results show that various reinforcement methods can achieve the expected reinforcement effect.In addition,the paper uses the Simple Scalar simulator and Cacti simulator to evaluate the power consumption,area,and performance overhead of different reinforcement methods.The simulation results show that the redundancy backup hardening strategy has a small impact on performance,because the redundant backup hardening method only introduces additional clock cycles when dealing with dirty Cacheline and data errors,and does not introduce additional clock cycles in other cases.The parity check and Hamming code error correction methods introduce delay overhead and increase the clock period.In addition,the parity check method can only detect errors,cannot correct errors,and has limited application scope;Hamming codes can correct errors,but the error correction ability is small.And it will introduce a large delay overhead;compared with the parity check and Hamming code error correction methods,the redundant backup method has the advantages of small delay overhead and error detection and correction.In order to apply to the system that is sensitive to performance,power consumption and area,this paper further optimizes the reinforcement strategy of redundant backup,and proposes a reinforcement strategy of partial backup.Simulation results show that the partial backup hardening strategy can improve performance and reduce power consumption.
Keywords/Search Tags:Multiple bits upsets, Cache system, Interleaved parity, redundancy backup, partial replication
PDF Full Text Request
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