Design Of Successive Approximation Register ADC In MEMS Accelerometer

With the birth of MEMS inertial devices,they have been widel y used in many fields because of their unique advantages,such as small size,low power consumption,light weight and good durability.For the research of MEMS accelerometer,considering that the signal output of accelerometer will produce deviation with the change of peripheral temperature,it is important to measure the surrounding temperature and compensate according to a certain relationship.In the process of signal processing,digital signal has become the main signal processing method.In order to convert the sensed temperature analog signal into digital signal,it is important to design an analog-to-digital converter used in MEMS accelerometer for temperature compensation,considering the low requirements of accuracy,speed performance and SAR for the advantages of ADC in power consumption and area,successive approximation ADC is chosen as the research object.In this paper,a 12 bit successive approximation analog-to-digital converter is designed.The main body of the converter is a charge type SAR with segmented structure ADC,to improve the segmented structure,put the redundant capacitance from the original low-level capacitance array into the high-level capacitance array,to solve the problem of non integral multiple of the coupling capacitance,but at the same time,the accuracy of the comparator is improved a little bit.At the same time,the sampling scheme of the capacitance upper board is adopted,and the capacitance does not need to be set,so the first bit quantization of the analog-to-digital converter is not actually needed.With the participation of the capacitor array,one bit of capacitance can be saved to complete the conversion,so the high-level and low-level capacitor arrays are designed as 6-bit and 5-bit respectively.The switching scheme based on Vcm can reduce the power consumption of the circuit to a great extent.The comparator adopts two-stage cascade structure,which is controlled by the same clock and has no static power consumption.Blocking kickback noise by isolating input signal and output signal.In order to reduce the nonlinearity of the sampling signal,the gate voltage bootstrap switch is used.The voltage band gap reference with second-order curvature compensation is selected.The temperature drift is 8.718ppm/?.The successive approximation logic is composed of D flip-flop.The timing logic is designed as the control end of each digital logic connected with the capacitor,the signal generator triggers each bit register in turn when the rising edge of the clock arrives,accomplishes the storage of each bit quantization result and the level switching of the capacitor sub board.Because the level switching of the capacitor sub board does not involve the signal distortion,CMOS switches are used.For the whole circuit simulation,when the sampling frequency is 5k Hz,the power consumption of the circuit is 115.25 u W,the signal-to-noise ratio is 63.43 d B,and the effective bit is 10.24 bits.