Design And Verification Of Fast Charging Control System Based On USB PD Protocol

With the rapid development of smart devices,the diversification of device functions has also been significantly improved,but the accompanying power consumption and insufficient battery life of mobile phones have become a hot issue in the field of development.How to improve the charging efficiency in a short period of time and at the same time extend the life of the mobile phone battery is the key to solving the poor power supply of smart devices.To shorten the charging time,it is necessary to increase the charging power.The USB PD protocol launched by the USB_IF association can meet this requirement,and the maximum power reaches 100 W,which can meet the requirements of most intelligent devices.Therefore,the research on USB PD is quite meaningful.This article describes the system framework of the USB PD protocol,and designs a fast charging system based on the USB PD protocol through atomic message sequences and data packet format transmission.The main content of the paper is as follows:1.The concept of Type-C interface and the communication process with PD protocol are introduced.The hierarchical structure of the system is analyzed,including the physical layer,protocol layer,policy engine layer,and device management layer.2.The USB PD protocol architecture and the communication mechanism based on the original message sequence are elaborated in detail.Using the hardware description language,a USB PD protocol fast charging control system is designed.The system is divided into a physical layer,a protocol layer,a policy engine layer,and a device management layer.The physical layer of the system is divided into a data receiving module and a data sending module: The data sending module needs to perform 4b/5b encoding,BMC encoding and CRC encoding calculation on the data;the data receiving module needs to perform CRC decoding check,BMC decoding,and 4b/5b decoding on the data.In order to enhance the robustness of the circuit,BMC decoding uses FIR filter algorithm,moving average filter algorithm,real-time correction circuit.The system protocol layer uses a three-stage state machine to implement message construction,message sending,message reception,and GoodCRC message reply functions;the system strategy engine layer uses a finite state machine to complete the communication control function based on the original message sequence;The device management layer includes the configuration of power capability,power negotiation,power supply and power hard reset.3.Build a simulation environment and perform simulation from the module level to the system level.The simulation results show that the system can perform fast charging and the maximum charging power can reach 100 W.In addition,power level switching in Fix mode,power level switching in PPS mode,and power level switching between Fix mode and PPS mode can be performed.4.The test environment is built by FPGA,and the test results show that the discharge power is dynamically output in the range of 0-33 W,which achieves the expected fast charging target.In the circuit conversion and implementation,Synopsys’ comprehensive tool DC is used for timing constraints,and the RTL code is converted into a gate-level netlist.DFT technology is used to insert a scan register in the gate-level netlist.To increase scan coverage,TestPoint technology is used.Make the scan coverage rate reach 96.49%.Finally,the static timing analysis of the circuit is completed,and all timing paths have no violations of the setup time and hold time.