Reasearch On The Modeling Method Of FPGA

FPGA study in academic filed mainly focuses on chip architecture,and rarely care manufacture technology and actual production.Because the research object of academic FPGA CAD software is abstract FPGA,and the abstract chip is with single architecture,few resources and simplified wiring resources,it's hard to use the academic CAD software to design and develop the real commercial FPGA chips with large scale,multi-granularity and complex wiring resources.There are two difficulties in applying the academic CAD software to practical chips:the way to model the actual chips and transforming the results of the academic tools into bitstream.After an in-depth study with academic and commercial FPGA CAD software,this paper comes up with a set of scheme of designing and developing the actual FPGA with academic CAD software.Three key technologies are designed to solve the two difficulties in the scheme.In this paper,the scheme is introduced in detail,and three key technologies are studied and implemented for the Virtex5 FPGA of Xilinx company.1)Modeling the real chip:The chip data information comes from the datasheet,user guider and chip information produced by Torc.2)Generating the wiring resource map of real chip:the wiring resource information is acquired from the chip database file and the C++ library provided by the third party tool Torc,and the wiring-diagram generation tool of the chip is realized in C++ language.3)Extracting the net-table information after the processing of the academic tool:Based on the third party tool Torc's chip database file and the class library,implementing the net-table information extraction tool in C++ language.This paper also tests the correctness and usability of the chip model files,wiring-diagram generation tools and net-table information extraction tools,and the results verify the feasibility of the scheme.Finally,we compare the running time of packaging and layout in VPR and ISE through experiments.The test results show that the total time of packaging and layout phase in ISE is about 11% faster than VPR when a larger circuit is designed.