Design And Implementation Of Cortex-M3 Integer Division Components

With the development of the chip's manufacturing technology and the society's blossom,the demand of the Embedded Equipment is soaring,the design of embedded chip is facing more and more challenges.Cortex-M3 is one of the most popular embedded processors recently,which has pretty excellent performance,less area and power consumption.It not only has a hardware multiplier,but also has a 32 bit hardware integer division.it can execute signed and unsigned division instruction.The Goldschmidt iterative algorithm has a quadratic convergence speed,which has known division algorithm recently.This Thesis based on Goldschmidt Iterative division algorithm,design and implementation a 32 bit integer divider for Cortex-M3 Embedded Microprocessor in ARMv7 project.This thesis elaborate the mathematical theory of Goldschmidt algorithm,analysis its quadratic convergence speed,build the mathematical model and optimize the circuit.Goldschmidt Iterative Algorithm multiply Numerator(N)and Denominator(D)with a series same iteration factors(F),making the Denominator tends to 1,Numerator tend to Quotient(Q).This thesis analyze the division instruction datapath,adopting the top-down design scheme to design the Division-unit.Using SystemVerilog Hardware Description Language is to design the RTL code.After realizing the Division-uint,based on the SVA and Constraint Random simulation verification method to complete the function verification.Demonstrate its quadratic convergence speed.After synthesis,it passed the gate-level netlist formal verification and post-simulation.This thesis design an integer divider for the Cortex-M3 based on the Goldschmidt algorithm.After finishing all designs,the paper can be summarized,using the Goldschmidt algorithm in Cortex-M3,the area and power completely meet the requirements of engineering,only need 1~10 clock cycle to complete a 32 bit integer division instruction.