| This thesis investigates design issues of high speed and low power circuit design using CNTFET Technology. In this thesis modeling and performance benchmarking for nanoscale devices and circuits have been performed for both nanoscale CMOS and carbon nanotube field effect transistor (CNFETs) technologies. Carbon nanotubes with their superior transport properties, excellent thermal conductivities, and high current drivability turned out to be a potential alternative device to the bulk CMOS technology. However, the CNFET technology has new parameters and characteristics which determine the performances such as current driving capability, speed, power consumption and area of circuits. As a result, new design methodology is needed to optimize performances.;This research presents a development of systematic design method to optimize circuit speed and power consumption. The optimization methods are different from traditional CMOS circuit design and characteristics of circuits. In this thesis, as a demand for these circumstances, three optimization methods are proposed and some traditional CMOS circuits are modified for CNFET and CNT interconnect technologies. The optimization methods explored in this thesis include digital circuit design, memory circuit design and high speed on chip I/O circuits.;In order to test the effectiveness of the design method, CNFET and CNT interconnect models have been developed and extensive HSPICE simulations have been performed in realistic environments considering screening effects, various noises and PVT variation. The simulation results show that proposed methodologies and modified circuits performed high speed and consumed low power compared to non-optimized and traditional circuits. |
