| The successful pursuit of the Moore's-law in the semiconductor industry has enabled the integration of highly complex functionalities on a single chip, thus enabling the proliferation of electronic devices in every spectrum of daily life. A new genre of such devices is wireless electronics (smart phones, netbooks, etc.) for mobile applications. However, the advent of Nano- CMOS (CMOS technologies below 90 nm) has brought new challenges for design, process, and test engineers. Soft errors have become a major reliability concern. These errors occur because of the combined effects of atmospheric radiation, and reduced noise margins. Another challenge is process variation that results in large spread in the delay and power distribution of circuits, and results in parametric yield loss. System power consumption is another major design challenge in Nano-CMOS because of high integration of transistors within a single chip and high amount of leakage current.;This thesis presents circuit-level techniques for soft error mitigation, low-power design with performance trade-off, and variation-tolerant low-power design. The proposed techniques can be divided into two broad categories. First, error compensation techniques are presented, which are used for soft error mitigation and also for low-power operation (with the help of guided circuitry as explained in next chapters) of linear and non-linear filters. Second, a framework for variation-tolerant low-power operation of wireless devices is presented. This framework analyzes the effects of circuit "tuning knobs" such as voltage, frequency, wordlength precision, etc. on system performance, and power efficiency. Process variations are considered as well, and the best operating tuning knob levels are determined, which results in maximum system wide power savings while keeping the system performance within acceptable limits. Different methods are presented for variation-tolerant and power-efficient wireless communication. |
