Evaluation of the architectural design for digital camera applications

The digital camera is in its booming stage of development. Many companies both in software, hardware, and digital imaging fields are plunging onto the digital camera bandwagon. This thesis surveys the core technologies that make digital cameras possible in the consumer market today. These core technologies include CCD image capture, image compression techniques, convergence of embedded DSP processor and RISC processor, high speed I/O design and memory storage device. We compare some of the general-purpose architectural designs from various manufacturers that include most of these features. Furthermore, we propose an architectural design that is suitable for both still camera and motion camera applications with state-of-the-art multimedia I/O design features. Lastly, we simulate a 16-bit RISC core processor in HDL. The simulation is a subset of the R2000 MIPS architecture that has instruction sets relevant to digital camera applications.