Design and implementation of a floating point multiplier using Altera's design environment and FPGA

In this thesis the design of a 16-bit floating point multiplier using Altera's design environment MAX+PLUS II (Multiple Array MatriX Programmable Logic User System II) and its implementation using FPGAs (Field Programmable Gate Arrays) is presented. The multiplier is designed with Altera Hardware Descriptive Language (AHDL) and Very High Speed Integrated Circuit Descriptive Language (VHDL) where the former is fully supported and the later only partially supported by MAX+PLUS II. The add-shift multiplication algorithm is used for the implementation and its area usage and performance is reported. Booth's radix algorithms are used as a discussion for improvements in speed but with tradeoffs on area usage.