Retiming and resynthesis approach for soft intellectual property integration in system-on-chip design

As we move into Deep Sub-Micron (DSM) feature sizes, the ability to build a System-on-Chip (SoC) is becoming more of a reality. To handle associated design concerns for these large and complex systems such as the need for high productivity as well as related technological issues that industry will face such as providing predictable circuit behavior, the computer-aided design (CAD) community has suggested a new design methodology. This methodology advocates the assembly of reused and therefore pre-characterized Intellectual Property (IP) components to build the system quickly and efficiently. The result is a great deal of replication and reuse culminating in solutions to the new DSM problems that are being faced.;But Current methodologies for building SoC designs from predesigned IP components suffer from inefficient system integration strategies. The focus of these assembly approaches is to make IP interfaces match during the process of integration with little regard to design metrics of the resulting systems as a whole. Their main objective is to initially get the functionality right which unfortunately may result in overhead due to added interfaces that in turn put into effect dramatic losses in other design metrics including performance, power, and area.;In order to improve the quality and success rate of the IP assembly process, we propose an integration approach that performs inter-IP optimizations during the assembly process. This approach includes retiming and resynthesis for soft IPs at a higher level of abstraction that takes the environment into account during the optimization phase. Results of designs under study show the effectiveness of such an approach. The ultimate goal of this work is the creation of an assembly strategy that improves productivity without sacrificing efficiency.