Research On Successive Approximation Register Analog-to-digital Converter Design And Single Event Transient Effects Hardening Techniques

With the continuous development of science and technology,China’s aerospace industry has dared to make great progress.With the establishment and expansion of space stations,space research and exploration activities have become more frequent,and the acquisition and conversion of various signals require high precision and high reliability.Successive Approximation Register Analog-to-Digital Converter(SAR ADC)with the characteristics of high precision and low power consumption are the first choice for aerospace applications and have become a hot research topic in recent years.However,the high-performance analog and mixed-signal circuits are sensitive to the frontal radiation effects.Radiation hardening is very difficult;analyzing and hardening are the key point to enhance reliability.Many key technologies need to be broken in the SAR ADC design and radiation hardening.Studies have shown that with the continuous advancement of semiconductor progress technology,Single Event Transient(SET)effect has become the main soft error source in integrated circuits.Anti-radiation hardening is essential to ensure the performance and reliability of SAR ADC.Combined with the common SET radiation hardening technology,this paper proposed a SET hardening technology for SAR ADC.At first,we designed a 12 bits 2MSPs sampling rate SAR ADC,simulating and analyzing the sensitivity of SAR ADC’s different modules to SET.Based on the module level and system level,presented radiation hardening method to meet the requirements of radiation resistance of the SAR ADC in practical applications improving the reliability of SAR ADC in radiation environment while considering its performance.Based on these works,the main research contents and innovations of this dissertation are as follows:(1)Proposed A digital foreground calibration algorithm based on a comparator to calibrate the comparator’s offset and the capacitance mismatch in the DAC capacitor array.Based on this,this paper designed a 12 bits 2MSPs sampling rate SAR ADC.The simulation results show that the differential nonlinear(DNL)and integrated nonlinear(INL)before calibration are-1.3/+1.5LSB and-13.1/+13.3LSB,DNL and INL after calibration are-0.64/+0.65 LSB and-1.1/+1.3LSB,respectively.After calibration,the Spur-Free Dynamic Range(SFDR)was improved from 54.52 d B to 84.45 d Bc,and the Effective Resolution Number of Bit(ENOB)was improved from 8.78 bits to11.08 bits.Both dynamic and static performance is significantly improved.(2)Proposed a background digital calibration algorithm based on the redundant capacitor array to calibrate the capacitor mismatch in the charge redistribution SAR ADC.Based on this method,a 12-bit resolution,2MSPs sampling rate SAR ADC is designed.Simulation results show that after calibration,the DNL changes from-1.1/+1.2LSB to-0.6/+0.7 LSB.The INL is decreased from-13/+13.1 LSB to-1.0/+1.1LSB.SFDR was increased by 24.13 d B from 61.50 d B to 85.63 d B.ENOB has been increased from 8.23 bits to 11.36 bits.The total power consumption of the test chip is 0.3564 m W,of which the digital background calibration module accounts for 6% of the overall power consumption,and its Figure-of-Merit(Fo M)is 67.80 f J/ Conv-step.(3)Proposed an Independent Piece-Wise Linear(IPWL)current source fault injection method to describe the Single Event Transient(SET)process more accurately.The sensitivity analysis of the SET effect is carried out on each SAR ADC module at the circuit level.It is found that the SET effect in the comparator and SAR control logic has the greatest impact on the overall performance and is the key module of radiation hardening.(4)Proposed a module-level SET hardening by design scheme for dynamic comparator and SAR control logic.The pre-amplifier circuit of the comparator is hardened by subsection and auto-zero adjustment.Dual Interlocked storage Cell(DICE)structure is adopted to harden the comparator’s latch stage and D flip-flop of SAR control logic.The test results’ comparative analysis shows that the chip after the reinforcement has better radiation resistance,and the error rate is significantly lower than before.