Research On High Speed Embedded Test Technology

Complex embedded systems are widely used in the fields of automobile,naval vessels,aerospace,weaponry equipments and so on.They have extremely high requirements on reliability.Therefore,it is necessary to carry out the corresponding tests during their development and production period.This paper takes the application of aviation airborne weapons system as the background,and studies the high speed test technology and the test system design technology.With aviation bus1553 B test as a specific application case,this paper designs the test system for1553 B bus device based on the CPCIE bus and the DSP + FPGA architecture technology.First,this paper introduces the characteristics of a representative precision guided bomb in an aviation airborne weapons system and analyzes the requirements of its test technology.It mainly includes various types of interfaces communications test,such as RS232,RS422,1553 B.And it also includes various analog,digital signal test.Second,regarding the 1553 B bus test as the specific application case and based on the test requirements of the military standard GJB5186-97 for the development and production of 1553 B bus,this paper analyzes the technical requirements of 1553 B bus test.This paper proposes the design of the test system for 1553 B bus equipment,including the protocol analysis unit,the impedance test unit,the signal acquisition unit,the signal generation unit and the data processing unit.Then,this paper outlines the circuit design of the power supply,clock and memory in the smallest system and the circuit design of the 1553 B protocol analysis unit which is necessary to implement the bus test.This paper mainly studies the design and implementation of the highspeed data processing parallel model,the CPCIE bus architecture and implementation of the high-speed test system,the high-speed communication design of the test system and the design of the signal acquisition module and the signal generation module.Last,according to the 1553 B bus test requirements of the GJB5186-97,the corresponding test and verification are carried out on the test system.This paper does the research on the the design and implementation of the high-speed data processing parallel model.A multi-core DSP parallel task model suitable for the test system is established to achieve high-speed data parallel processing.This paper does the research on the high-speed communication design of the test system,including the CPCIE bus architecture and implementation,and the communication principle,communication speed of the SRIO and the Ethernet and so on.This paper does the research on the signal acquisition and signal generation technology.The high speed Analog to Digital converter is used to acquire 1553 B signal and analysis of waveform characters.The high speed Digital to Analog converter is used to generate the signal to achieve 1553 B bus test excitation signal injection.This paper studies the high speed embedded test technology,which has certain reference value for realizing high speed test of the complex embedded system.