Research On An Error Test Method For High Speed Maglev Train Vehicle-Ground Communication System

In a communication system,the bit error rate is an important indicator to measure the transmission quality of a communication system,and the bit error test at the receiving end of the device under test can evaluate the transmission quality of the communication system.For high-speed maglev trains,the communication system between train and ground is the only communication bridge between the train and the ground.The reliability of vehicle-ground data transmission directly affects driving safety.Therefore,it is important to accurately evaluate the transmission quality of the communication system.High-speed maglev trains need to exchange a variety of business information with the ground.These information are communicated through multiple simultaneous RS-485 and Ethernet interfaces.The communication protocol is a customized protocol.General error testing equipment is not suitable for testing high-speed maglev train vehicle-ground communication system.The vehicle-ground communication system has practical engineering significance for the research and implementation of the error test method of the vehicle-ground communication system.This thesis aims to design an error test system dedicated to testing the high-speed maglev train vehicle-ground communication system,and the main research contents are as follows:1.Based on the test model used in the wireless communication system and the basic principles of error testing,a special error testing method for testing the high-speed maglev train vehicle-ground communication system is proposed.2.Considering the design principle and system architecture of the error code test system,the design scheme of the error code test system based on the ARM processor and FPGA is determined.ARM processor has the advantages of fast processing speed,strong compatibility and low power consumption.It mainly completes the error test of Ethernet interface communication and data processing and system control;FPGA has the advantages of strong flexibility,parallel operation and convenient testing.Complete the error test and data processing of the synchronous RS-485 interface communication.3.The hardware design of the error code test system is completed.Including package library drawing,device selection,PCB layout drawing,schematic design and hardware debugging.4.The software design of the error code test system is completed.Including FPGA and ARM program development and other work.FPGA program development is based on the integrated design and development environment software Vivado and Verilog HDL language,which realizes the functions of pattern generation,synchronous RS-485 transmission and reception,error detection and SPI communication.ARM program development is based on the Keil C51 platform,and the functions of data processing,network data receiving and sending,and error detection are realized.In addition,this article also completed the design of the touch screen interface and realized the interactive function.5.The functional test of each module of the error test system was carried out,and a test platform was built according to the test method,and the whole machine test of the error test system was carried out.