Design Of A High-PSR Low Dropout Regulator

With the popularity of portable electronic devices,the market demand for power management chips is increasing.Low dropout regulator(LDO)is widely used in system on chip(SOC)for its advantages of small output ripple,low noise and small chip area.But with the continuous progress of semiconductor technology,the power supply voltage is getting lower and lower.The system on chip is more and more sensitive to the noise ripple of power supply voltage,especially the analog and RF modules.In order to improve the ability of PSR,the research of LDO with high PSR becomes more and more popular.In this thesis,by analyzing the basic working principle of LDO,combined with the current research hotspot of high-performance LDO,a high PSR capacitor less LDO is designed.Based on the detailed derivation of the ripple transmission path of LDO power supply,this thesis proposes two ways to improve the performance of LDO PSR:(1)the current mode feed-forward ripple elimination technology is used to keep the gate source voltage difference constant,so as to reduce the influence of ripple noise on the output voltage;(2)the error amplifier with folded cascode structure is used to make LDO have very high loop gain.In addition,in order to solve the stability problem of LDO without off chip capacitor,pole separation technique and Miller compensation are used to make the circuit work stably without off chip capacitor.The design of this thesis and circuit implementation is based on TSMC 40 nm BCD process,and LDO is simulated in detail by cadence spectre.The simulation results show that the output voltage of LDO is stable at 1.75 V when the input power supply voltage is between 2V and 2.7V.Under different load conditions,the phase margin is always above 60 degrees.The PSR is-98 d B at low frequency and-67 d B at 1 MHz.The linear voltage difference is less than 180 MV and the quiescent current is 210 μA.