| In recent years,with the increasing integration of System on Chip(So C),interference between digital-analog mixed circuits and power supply noise has become more and more serious,so the performance requirements for power management units are also increasing.In addition,the widespread application of electronic products makes the chip functions increase,and the power supply needs to drive larger loads,and the increase of load range will bring difficulties to the frequency compensation of the system.Therefore,designing a power management unit with high power supply rejection ratio(PSRR)and stable output in a wide load range is of great practical significance.For the currently popular smart bracelet working scenario and principle,a dual-channel output power management unit is designed.The low voltage difference linear regulator of Channel 1 is mainly used to power the analog module.In order to solve the power interference and crosstalk between modules,a three-stage amplifier circuit is adopted to increase the power suppression ratio of LDO and improve the linear adjustment rate of LDO.In order to make the system stable in the full load range,a dual zero point compensation technology is proposed through detailed analysis of the zero point in the system.By controlling the distribution of zero points under different loads,the phase margin is improved,and a reliable compensation scheme is provided for LDO design.Considering that the current driven by LDO may exceed 300 m A,and there may be short circuit causing chip temperature rise,an overcurrent protection circuit and an overtemperature protection circuit are designed to protect the chip.Additionally,Channel 2 is a voltage regulator circuit for supplying power to the digital module.In order to save the area on the chip,a voltage regulator without external capacitor structure is adopted.At the same time,in order to solve the problem of small power consumption but large ripple of digital module,a voltage regulator structure with NMOS as power tube is adopted to greatly improve the power supply suppression ratio of Channel 2 voltage regulator.Finally,in order to solve the problem of poor transient response of no external capacitor,a transient enhancement circuit is adopted to improve the transient response performance and make the voltage regulator more stable and reliable.On the Cadence Virtuoso platform,circuit design and simulation verification were completed using TSMC180 nm CMOS process and Spectre simulation tool.The simulation results show that,with the double zero-point compensation network,the LDO of channel 1 can achieve a stable output of 1.5 V in the load range of 300 m A under the simulation conditions of 3V power supply voltage,tt＿corner and 27 ℃;the power suppression ratio can reach 98 d B in the low frequency band and 72 d B at 1 k Hz;it can achieve 152 ℃ over-temperature protection and 377 m A over-current protection function.The linear regulator of channel 2 consumes a total of 3.4u A static current,and can stably output 1.5 V voltage within the load range of 1m A under the simulation conditions of 3V power supply voltage,tt＿corner and 27 ℃.The power suppression ratio can reach 102 d B in the low frequency band and 98 d B at 1 k Hz,meeting the design specifications.During layout design,differential pairs are arranged in a center-symmetric structure to reduce common mode noise,and bipolar transistors with gap reference are placed in a center-symmetric structure to reduce current mismatch.Finally,post-simulation verification of LDO was completed,and the simulation results show that the power management unit has good performance.Figure 65 Table 7... |
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