Research And Design Of Low Dropout Linear Regulated Power Supply With Low Noise And High Power Rejection Ratio

With the expansion of consumer electronics market,the performance requirements of power management chips are higher and higher.Such as noise,power rejection ratio,integration,transient response,power consumption and other key indicators have higher requirements.Especially with the popularity of 5G,in some RF chips and some special circuits such as AD/DA and oscillator,the interference between signals can easily affect the working state of the circuit.Therefore,the power supply is generally required to be"clean",so there are further requirements for the noise and rejection ratio of the power supply^[1].Therefore,the research of low dropout regulator with low noise and high power supply rejection ratio is of great significance to the practical application of power management chip.According to the application requirements of low dropout regulator with low noise and high power supply rejection ratio,based on the classical NMOS LDO,this paper adopts the adaptive gain control module to mirror the K1 times of the output current to the automatic gain control module to form a feedforward path.A ripple component is introduced to offset the power ripple from the forward input to the output through the summation circuit buffer,so as to improve the power supply rejection ratio of LDO under different load conditions.On this basis,in order to reduce the impact of long transient response time caused by off chip load capacitance,an adaptive transient enhancement circuit is introduced to mirror K2 times of the output current to the error amplifier.By increasing the current of the error amplifier and increasing the low-frequency gain,the transient response time of LDO is reduced.At the same time,it makes LDO have higher low frequency PSRR under the same load condition.This design adopts SMIC with deep-n-well CMOS 0.18μm process realizes circuit simulation,layout design and tape out.The core area of the chip is 368*460μm^2.By analyzing the advantages and disadvantages of different test methods,select the appropriate test scheme,and make the test circuit.Simulation shows that the application of Feed Forward Ripple Cancellation loop in this design improves the PSRR by 30 d B.Finally,the maximum chip noise is 12.7μV/（?）.When the frequency is 1Hz to 100 Hz,the circuit noise is less than 134 n V/（?）.Under 100μA current load,when the frequency is<1 MHz,the PSRR is>-74 d B;Under 100 m A current load,when the frequency is<100 KHz,the PSRR is>-82 d B,when the frequency range is100 KHz-1 MHz,the PSRR is>-59 d B.The index meets the requirement.