Image Quality Improvement Algorithm Research And FPGA Implementation For Intelligent Traffic

The image quality of the intelligent railway monitoring system determines the accuracy of the subsequent intelligent algorithm.Taking a railway project of a company as an example,this project introduces the structure and field installation of the railway sweeping system,explains the device selection of wire-array camera and completes the general block diagram of hardware circuit in detailIn view of the obvious vertical fringe phenomenon of GL0402 imaging effect,a uniform light cylinder was used to set up an experimental environment to collect a large number of image samples and optimize the mean filtering algorithm.After that,the sensor’s photosensitive response was linear.Compared the advantages and disadvantages of two-point method and piecewise linear method,proposed two-point method FPN correction algorithm and Matlab simulation verification,from the main/objective evaluation of the algorithm effect improved significantly.Design hardware circuit framework,focus on Avalon from interface,floating point fixedpoint and data cross-clock processing scheme.As the imaging quality is limited by the line frequency matching degree,the requirement of line frequency real-time accuracy is proposed,and the radar module is selected as the research object.As the traditional three-dimensional space vector transformation to calculate the radar velocity to the acquisition of horizontal frequency conversion coefficient not inaccurately,based on the principle of image deformation line frequency adaptive correction algorithm,and set up the experimental platform of sample image simulation verification,to prove the feasibility of the algorithm,thus detailed algorithm process and the FPGA module design.The row cache designed in the algorithm was optimized,and a parallel row cache structure was adopted.The Line Buffer row cache module was designed by calling the primitive instead of directly calling RAM to maximize the resource utilization,reduce the synthesis time and improve the efficiency by pre-determining the memory size.