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A Design Of Fast Response Digital Low Dropout Regulator Based On Enhanced Analog Assisted Loop

Posted on:2022-09-08Degree:MasterType:Thesis
Country:ChinaCandidate:R P ChenFull Text:PDF
GTID:2492306569972589Subject:Microelectronics and Solid State Electronics
Abstract/Summary:PDF Full Text Request
The digital low dropout(DLDO)regulator can work effectively in subthreshold supply voltage.It is basically composed of synthesizable digital circuits,resulting in a good process scalability.These advantages can make up for the shortcomings of analog LDOs in terms of power consumption and chip area.Therefore,DLDOs are highly attractive.However,a poor transient response is happened in DLDOs caused by the limited sampling clock.When using slow clock,as a fast load transient coming,a sharp droop is produced in output voltage.In order to break down the trade-off between speed and power,a DLDO based on enhanced analog assisted(E-AA)loop is proposed to get rid of clock control.The E-AA loop is out of clock control and has a faster transient response on the basis of the original digital loop.The loop gain is maximized by using a current buffer while maintaining system stability.In the E-AA loop mentioned above,the coupling capacitor is large.If a small capacitor is used,a second droop in the output voltage is happened during recovery.In order to comply with the DLDO design trend of small capacitors,a switch compensation resistor technique is added in E-AA loop.In transient state,the time constant of the loop is increased to prevent a second droop of output voltage.At the same time the value of the coupling capacitor is reduced.In the digital loop,a technique of coarse fine tunning(CFT)is presented for better performance.During recovery of output voltage,the E-AA loop is gradually invalid,and the coarse tunning control is activated for faster recovery.In the steady state,the fine tunning control is activated for suppressing output ripple.Under the TSMC 65nm CMOS process,the simulation results of the DLDO are good.When the Input voltage VIN is 0.6V and the sampling frequency FS is 10MHz,VOUT=0.5V is realized.In the transient step response ofΔILOAD=4m A~9m A/3.8ns,the undershootΔVDROOP is26.1m V,the settling time TR is 14ms,and the Current efficiencyηis 99.1%at 9m A,the total capacitance CTOTis 52p F.The figure of merit(Fo M)is 0.72ps.
Keywords/Search Tags:Digital Low Dropout Regulators, Enhanced Analog Assisted Loop, Current Buffer, Switch Compensated Resistor, Coarse Fine Tunning
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