A Low Power Digital Low Dropout Regulator With Adaptive Coarse/fine Regulation Control

Low dropout regulator play a crucial role in System-on-Chip designs.With the continuous advancement of chip fabrication processes,electronic devices such as flash memory and image sensors require Low dropout regulator with low output voltages to provide stable power,enabling higher energy efficiency and longer battery life.Compared to analog low dropout regulator,Digital low dropout regulator have the advantages of low voltage operation,insensitivity to temperature,less chip area occupied.So the design of digital low dropout regulators with better performance has become a hot research topic.To address the common issue of limit-cycle oscillations in digital low dropout regulators,this paper presents a detailed theoretical analysis of limit-loop oscillation using phase analysis.By introducing appropriate phase delay or lead,the phase characteristics of the system can be altered to suppress limit-cycle oscillations.The phase hysteresis of conventional and digital low dropout regulators with digital feedforward compensation is compared and analyzed for different limit-loop oscillation modes and different frequencies,and the output does not change when the phase varies within a certain range,from which the boundary conditions of the limit-loop oscillation modes can be obtained.Next,the ripple magnitudes under different load capacitances and different limit-loop oscillation modes are compared and analyzed to conclude that the ripple magnitudes and oscillation modes jump under specific load capacitances.In order to improve the transient response,this paper proposes a low power digital low dropout regulator with adaptive coarse and fine regulation based on the previous analysis of limit-loop oscillation,which enhances the response speed and shortens the recovery time of the system.The circuit mainly consists of a dynamic comparator,bidirectional shift register,switch array,signal detection circuit,and clock signal conversion circuit.When the load undergoes significant transient changes,conventional digital low dropout regulators suffer from long recovery times.Therefore,this article proposes a signal detection circuit and clock signal circuit to achieve adaptive adjustment of the clock signal,thereby enabling fine-tuning of the circuit.The signal detection circuit determines the presence of continuous signals based on the output of the dynamic comparator.This signal is then transmitted to the clock signal conversion circuit,which dynamically generates a clock signal with double rising edges.This increases the feedback gain,allowing control over the number of PMOS transistors that are turned on in the switch array during the shift register cycle.This operation puts the circuit in coarse adjustment mode,thereby accelerating the transient response.As a result,the circuit can quickly recover to a stable state within a short period of time,transitioning into fine-tuning mode.Additionally,the circuit design avoids the saturation problem of bidirectional shift registers,while improving the recovery speed and thus the transient response,making it more widely applicable in various electronic devices.This paper is based on the SMIC 180 nm process and utilizes the Cadence Virtuoso platform to design and simulate each module of the proposed circuit,as well as validate the overall circuit performance.The circuit layout design and subsequent post-simulation were also completed.With an input voltage of 0.9 V and a reference voltage of 0.85 V,under a load current transition from 300 μA to 600 μA within a time period of 5 ns,the output voltage exhibits an undershoot of 52 m V and a recovery time of 1.9 μs.The overshoot is 26 m V with a recovery time of 2.28 μs.The voltage difference is 50 m V,and the linear adjustment rate is 8.89 m V/V.The load adjustment rate is 1.56 m V/m A.The circuit achieves a maximum current efficiency of 99.8%.The circuit occupies an area of 233 μm × 146 μm and exhibits overall good performance.