Design And Implementation Of Broadband Power Line Carrier Communication Test System Based On ZYNQ

Power Line Communication(PLC)utilizes existing power lines for communication.With the advent of the Internet of Things era,PLC technology is more and more widely applied.State Grid is vigorously promoting the construction of the ubiquitous power Internet of Things based on PLC technology.At the same time,Huawei has also launched a novel intelligent home system based on PLC technology.However,a lot of interference will be generated during PLC communication due to the poor power line channel.Orthogonal Frequency Division Multiplexing(OFDM)is widely used in the new generation of PLC technology due to its excellent anti-interference ability and ultra-high frequency band utilization.Based on the laboratory project,this paper designs and implements a Low-Voltage Broadband Power Line Carrier Communication(BPLC)test system with the ZYNQ platform on the basis of the National Grid broadband power line carrier communication standard protocol.The main tasks are as follows:1.Introduce the detail information on the low-voltage power line channel characteristics,OFDM technology and BPLC layer protocols;determine the overall system framework according to the functional requirements and performance index requirements of the BPLC test system;and design a specific terminal implementation plan based on the ZYNQ platform,including hardware and the software implementation plan.The scheme completes the development of the main functions of the system on ZYNQ,simplifies the system development process and reduce the difficulty of debugging.Additionally,it can also carry out the coordinated development of software and hardware,with good flexibility.2.As for the hardware part,the design and implementation process of the key modules of the physical layer,the data acquisition and the overall scheme of the hardware system are explained in detail.For the part of the symbol synchronization at the receiving end in the physical layer,the original symbol synchronization algorithm is improved to enhance the symbol synchronization performance while reducing the consumption of hardware resources,according to the actual situation of the project and the structure of the leading symbol.In the realization of dual binary Turbo decoding,the whole decoding process can be completed with only one sub-decoder module by reasonably arranging the circuit structure,which saves a lot of hardware resources.3.As for the software part,firstly,uses Xilinx’s Peta Linux tool on the basis of the hardware part to quickly complete the Linux system migration of the hardware platform;then,develops the AXI DMA IP core Linux device driver to realize the high-speed data transmission of the data link layer and physical layer of the BPLC test system.Finally,multithreading technology is used to complete the development of TCP server threads,data receiving and processing threads and clock threads.4.Build a test platform to test the physical layer protocol conformance and communication performance of the designed system.The test results show that the system basically meets the functional requirements and performance index requirements of the project.