Design And Implementation Of Simultaneous Sampling And Data Transmission Module In Oscilloscope Power Analyzer

The oscilloscope power analyzer plays a very important role in the monitoring of complex power systems as an instrument with both waveform display and high-precision power calculation functions.The stable transmission of multi-channel data in the oscilloscope power analyzer and the accuracy of power analysis are inseparable from the synchronous data sampling processing;in different application scenarios,due to different sampling rates and resolutions,the transmission data bandwidth is not fixed.The module also puts forward high requirements on transmission speed and stability,and the effects of these two parts affect the performance of the entire instrument.Therefore,this thesis is written from the perspective of improving the stability and versatility of data synchronous sampling and realizing data transmission between FPGA and DSP.The main research contents are as follows:1.In view of the oscilloscope power analyzer’s demand for high-precision measurement of power parameters,this thesis uses full-cycle simultaneous sampling to reduce the error caused by spectral leakage during FFT operation.The synchronous sampling clock generation module is designed and implemented,which saves 50% of ADC resources compared with the traditional method,and reduces the transmission delay of the synchronous sampling clock;in addition,the transition protection function is introduced in the synchronous sampling clock generation process In order to prevent the synchronous sampling clock from shaking obviously due to the slight change of the frequency of the signal to be measured,the stability of the synchronous sampling clock is guaranteed.2.According to the different requirements for sampling data in the power mode of the oscilloscope power analyzer,a system architecture compatible with multiple sampling modes is designed and implemented,which can adapt to the buffering of the sampling data in the power mode.The power mode buffer module can adapt to the characteristics of variable sampling rate under the condition of synchronous sampling.The polling detection module is used to realize the control and judgment of the sending sequence of buffered data of each channel,so that the data of each channel can be sent in an autonomous and orderly manner without conflict.end module.The architecture can be adapted to the data requirements of multiple types,multiple numbers and different sampling rates of front-end acquisition boards,and has good versatility and portability.3.In view of the requirement of the oscilloscope power analyzer for continuous and uninterrupted power parameter calculation of a large amount of data,this thesis designs and implements the SRIO high-speed data transmission module between FPGA and DSP,and formulates the transmission of data flow according to the data requirements in power mode.Compared with the traditional method,the memory space division method can improve the efficiency of data interaction between FPGA and DSP;the SRIO protocol encapsulation module is designed,and the encapsulation module can automatically To adapt to the front-end transmission rate,the sampling data and its corresponding frequency and other information are automatically encoded and encapsulated through the state machine,and finally transmitted to the DSP through SRIO.After testing,the synchronous sampling and data transmission module of the data can achieve 5120 data points per frame,and the three sampling boards work continuously for 24 hours in a synchronous sampling mode.The stable sampling transmission of data.