Research On Low Power Physical Design Of CPU Module Based On 7nm Process

With the constantly development of integrated circuit technology,the feature size can be achieved with nanoscale,which causes the integration and performance of chips greatly improved.However,the faster and faster clock frequency will inevitably lead to an increase in power consumption.In addition to the performance and area of the chip,power consumption has become a more and more concerned design indicator.Reducing power consumption can not only extend battery life and bring a better experience to users,but also reduce thermal packaging costs and reduce additional cooling systems.With the rapid development of mobile terminals,low power solution has gradually become an important research direction of integrated circuit design.The research object of this article is a module in a multi-core CPU chip.The module contains 2 shut-off power domains and each of them can switch between 1.0V,0.8V,and off working modes.The scale of the module is about 2.46 million gates and the maximum operating frequency is 1.949 GHz.This article uses Unified Power Format to describe the low-power intent of the module.Using the Innovus tool of Cadence company achieved complete back-end physical design and power optimization of the module based on Samsung 7nm process.The mainly work and achievements of this thesis is below:Firstly,achieved the whole back-end physical design of the module based on netlist which is synthesized with UPF.During floorplan stage,chip shape and area,hard macro location,power switch location have all be determined.Then finished placement,clock tree synthesis route and optimization stage.Secondly,updated previous CTS flow by using early clock flow to achieve clock tree rather than using standard clock tree synthesis flow.The result proved that the performance of clock tree generated by early clock flow is better than standard flow.The Worst Negative Slack reduced from original-114 ps to 55 ps,with an optimization rate of 51.75%.The power consumption of clock net reduced from original 277.04 m V to 260.02 m W,with an optimization rate of 6.14%.Thirdly,updated previous global physical synthesis flow by using power aware global physical synthesis flow.First of all,finished the research on the influence about leakage To Dynamic Ratio to total power.The result shows that total power is minimum when leakage To Dynamic Ratio is set to 0.5.Next,finished the research on the influence about power optimization mode to total power.The total power generated by None mode will be regarded as reference.In High mode,the total power reduced from original1748.14 m W to 1448.90 m W,with an optimization rate of 17.12%.As for timing part,Setup WNS degraded 14 ps and Hold WNS degraded 7ps.In Low mode,the total power reduced from original 1748.14 m W to 1633.44 m W,with an optimization rate of 6.56%.As for timing part,Setup WNS degraded 5ps and Hold WNS degraded 3ps.In both High and Low mode,timing degradation caused by power optimization is acceptable,because only several picosecond can be fixed by timing ECO operation.The power optimization methods and results shows in this thesis can provide a technical reference for power optimization in advance design node.Choosing a suitable leachage To Dynamic Ratio and power optimization mode is helpful to achieve expected power and timing result.