The Verification Research Of Analog-to-Digital Converter Control Model Based On UVM

With the continuous development of integrated circuit technology,the difficulty and complexity of chip design have also increased.This makes the importance of chip verification in the chip design process continue to increase,and the time and resources invested in verification are also increasing.Efficient and guaranteed high completeness verification has become a great challenge in the integrated circuit industry.Based on the internship project of the internship company,the author completes the verification of the analog-to-digital converter control module.By studying the System Verilog language and Universal Verification Methodology,a verification platform is built,and the functional verification of the analog-to-digital converter control module is performed,which shows the advantages of the Universal Verification Methodology compared to traditional verification methods.The Design Under Verification verified in this article is an analog-to-digital conversion control module in a microcontroller chip independently developed by the author’s internship company.The chip contains three single-ended 12-bit high-speed successive approximation analog-to-digital converters,which are connected to the AHB bus via DUV.The generation,transmission,and processing of data,commands,and clock information between the AHB bus and the analog-to-digital converter are achieved through DUV.In this paper,the development history and current status of verification language and verification methodologies are firstly studied,and the advantages and characteristics of System Verilog and Universal Verification Methodology(UVM),as well as their advantages over traditional verification methods.Then I studied the So C system structure and AMBA AHB-Lite protocol.Through the study and analysis of the analog-to-digital converter control module,understand the specific functional characteristics,working mechanism and configuration information,extract detailed functional verification points,draw up specific testcases and basic sequences,and develop specific verification plan.Build a verification platform based on UVM.The specific components in the verification platform include: abb_system_env provided by the verification IP,register model: adc_regmodel,virtual sequence generator: abb_virtual_sequencer,DUV reference model: adc_model,agent: adc_agent,scoreboard: adc_scoreboard,and specific testcases and specific sequences etc.Different components have different functions.These components are instantiated in testcases and connected to each other.Simulation verification is performed using a randomized verification method with constraints.The verification results are analyzed.Functional coverage is collected through coverage modeling and collecting code coverage through tools,the final functional coverage reached 100%,and the code coverage was 93.66%,completing the verification work.Proof of verification work: Compared with traditional verification methods,the verification platform built in this paper can perform timely comparison and detection of data results,report error information in time,and automatically collect coverage,which greatly improves verification efficiency.Moreover,the verification platform is highly reusable,greatly reducing the time and resources consumed by the verification link,and has strong engineering practical significance,and has reference significance for the complicated problems of related IC verification.